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Introduce PMCR-based cpufreq(4) driver, for IBM POWER9 systems
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Authored by jhibbits on Jun 20 2018, 7:08 PM.

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Summary

POWER9 uses a single CPU register, per core, to change clock speed. Everything else is handled by the on-chip controller. This change necessitates a change to the cpufreq global kernel driver to bump supported levels, as the POWER9 device tree can have theoretically 256 different options. On my POWER9 Talos, the list consists of 100 items. At 16.67MHz intervals, that allows for a change of roughly 1.67GHz between lowest and highest.

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jhibbits created this revision.Jun 20 2018, 7:08 PM
nwhitehorn accepted this revision.Jun 21 2018, 4:56 AM

Looks good to me.

sys/powerpc/cpufreq/pmcr.c
129 ↗(On Diff #44175)

How POWER9-specific is this?

This revision is now accepted and ready to land.Jun 21 2018, 4:56 AM
jhibbits added inline comments.Jun 21 2018, 1:41 PM
sys/powerpc/cpufreq/pmcr.c
129 ↗(On Diff #44175)

Currently it's very specific, because of the masking involved. I just checked on the POWER8, and that device tree also does include the requisite properties, but the format appears different from the POWER9, so I'm reluctant at this time to open this up to that as well. Once I figure out the POWER8 format, I can make it work for that with this same driver.

This revision was automatically updated to reflect the committed changes.