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Add support for the XIVE XICS emulation mode for POWER9 systems

Authored by jhibbits on May 19 2018, 7:58 PM.



POWER9 systems use a new interrupt controller, XIVE, managed through OPAL
firmware calls. The OPAL firmware includes support for emulating the previous
generation XICS presentation layer in addition to a new "XIVE Exploitation"
mode. As a stopgap until we have XIVE exploitation mode, enable XICS emulation
mode so that we at least have an interrupt controller.

Since the CPPR is local to the current CPU, it cannot be updated for APs when
initializing on the BSP. This adds a new function, directly called by the
powernv platform code, to initialize the CPPR on AP bringup.

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Event Timeline

jhibbits created this revision.May 19 2018, 7:58 PM
nwhitehorn added inline comments.May 19 2018, 8:40 PM
99 ↗(On Diff #42743)

HVICE is a reserved bit on POWER8 (ISA 2.07) and should be set only on POWER9 (Power ISA 3+). This should probably be some switch on the ISA version from CPU features rather than the PVR, anyway.

406 ↗(On Diff #42743)

Ditto here with respect to POWER8.

238 ↗(On Diff #42743)

Note that this is only in ISA >= 3?

156 ↗(On Diff #42743)

See: POWER ISA 3 comments.

465 ↗(On Diff #42743)

This method is called only on APs, so no need for this if.

466 ↗(On Diff #42743)

Why not do this inline? I assume this whole mode will be removed once XIVE support lands.

563 ↗(On Diff #42743)

This is guaranteed to the be the root PIC. Why not rely on that?

jhibbits added inline comments.May 20 2018, 12:52 AM
99 ↗(On Diff #42743)

Easy enough to address. I'll set up a 'lpcr' variable at platform init time appropriate for the CPU (can use cpu_featuers at this point, since it's initialized much earlier than platform)

238 ↗(On Diff #42743)

Can do, will do

563 ↗(On Diff #42743)

True, I could do that. I went this route as a sort of seatbelt, but it's probably overkill.

jhibbits updated this revision to Diff 42751.May 20 2018, 2:00 AM

Address Nathan's comments

  • Use root_pic instead of locally stored PIC reference.
  • Create a lpcr variable to hold the LPCR config, which is different from 2.0x and 3.0.

See the comment on line 467 about powernv_smp_ap_init(). Otherwise, looks good.

157 ↗(On Diff #42751)

Shouldn't this be earlier/elsewhere? It's not exactly PowerNV specific (insofar as PowerNV means "opal + FDT"). This is not a blocking comment, though.

jhibbits updated this revision to Diff 42752.May 20 2018, 2:38 AM

Check the BSP by first getting the BSP, rather than relying on special knowledge.

nwhitehorn added inline comments.May 20 2018, 2:50 AM
157 ↗(On Diff #42752)

This double-sets LPCR_HVICE.

470 ↗(On Diff #42752)

This doesn't work. PCPU fields aren't set until after this function is called on the BSP.

jhibbits updated this revision to Diff 42753.May 20 2018, 3:07 AM

Address further comments

jhibbits updated this revision to Diff 42754.May 20 2018, 3:17 AM

Delete unnecessary bits

nwhitehorn accepted this revision.May 20 2018, 3:21 AM
This revision is now accepted and ready to land.May 20 2018, 3:21 AM
This revision was automatically updated to reflect the committed changes.