Add initial support for the floating point implementation register.

[jhb]

Summary

Add initial support for the floating point implementation register.

• Save the current FIR in the global 'cpuinfo' structure in a new 'fpu_id' member.
• Decode flags in the FIR when displaying other CPU flags during boot.
• Use the existing "dummy" slot in the floating point register structure to export the FIR in process core dumps and via ptrace().

Test Plan

• booted under qemu which displayed the following output:

cpu0: MIPS Technologies processor v160.130

MMU: Standard TLB, 48 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
L1 i-cache: 4 ways of 256 sets, 32 bytes per line
L1 d-cache: 4 ways of 256 sets, 32 bytes per line
L2 cache: disabled
Config1=0xdea3519b<PerfCount,WatchRegs,EJTAG,FPU>
FPU ID=0xf8200<S,D,PS,3D,W>
Config2=0x80000000

• with a patched gdb to pull 'fir' from current dummy slot in fpreg, was able to "see" value of fir for live process and from a core

[kan]

Any reason why it has to be part of registers? It is not volatile

[imp]

sys/mips/mips/swtch.S

534 ↗

(On Diff #28083)

Wrong name?

[jhb]

In D10617#220811, @kan wrote:

Any reason why it has to be part of registers? It is not volatile

This is how other OS's (Linux and NetBSD at least) export FIR. Creating a custom note in the core or a new ptrace op just to fetch FIR seems a bit much compared to this approach.

[kan]

.. but please fix the wrong comment text pointed out by Warner

[jhb]

sys/mips/mips/swtch.S

534 ↗

(On Diff #28083)

Will include fix in commit to svn.