[RISCV] Lower llvm.trap and llvm.debugtrap

Summary:
Until this commit, these have lowered to a call to abort().

`llvm.trap()` now lowers to `unimp`, which should trap on all systems.

`llvm.debugtrap()` now lowers to `ebreak`, which is exactly what this
instruction is for.

Reviewers: asb, luismarques

Reviewed By: asb

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69390

[ELF][PPC32] Fix canonical PLTs when the order does not match the PLT order

Reviewed By: Bdragon28

Differential Revision: https://reviews.llvm.org/D75394

[ELF][PPC32] Don't report "relocation refers to a discarded section"
for .got2

Similar to D63182 [ELF][PPC64] Don't report "relocation refers to a
discarded section" for .toc

Reviewed By: Bdragon28

Differential Revision: https://reviews.llvm.org/D75419

[EarlyCSE] avoid crashing when detecting min/max/abs patterns (PR41083)

As discussed in PR41083:
https://bugs.llvm.org/show_bug.cgi?id=41083
...we can assert/crash in EarlyCSE using the current hashing scheme
and instructions with flags.

ValueTracking's matchSelectPattern() may rely on overflow (nsw, etc)
or other flags when detecting patterns such as min/max/abs composed
of compare+select. But the value numbering / hashing mechanism used
by EarlyCSE intersects those flags to allow more CSE.

Several alternatives to solve this are discussed in the bug report.
This patch avoids the issue by doing simple matching of min/max/abs
patterns that never requires instruction flags. We give up some CSE
power because of that, but that is not expected to result in much
actual performance difference because InstCombine will canonicalize
these patterns when possible. It even has this comment for abs/nabs:

  /// Canonicalize all these variants to 1 pattern.
  /// This makes CSE more likely.

(And this patch adds PhaseOrdering tests to verify that the expected
transforms are still happening in the standard optimization
pipelines.

I left this code to use ValueTracking's "flavor" enum values, so we
don't have to change the callers' code. If we decide to go back to
using the ValueTracking call (by changing the hashing algorithm
instead), it should be obvious how to replace this chunk.

Differential Revision: https://reviews.llvm.org/D74285

  Fix -Wdeprecated-copy-dtor and -Wdeprecated-dynamic-exception-spec
  warnings.

  Summary:
  The former are like:

  libcxx/include/typeinfo:322:11: warning: definition of implicit copy
  constructor for 'bad_cast' is deprecated because it has a
  user-declared destructor [-Wdeprecated-copy-dtor]
    virtual ~bad_cast() _NOEXCEPT;
	    ^
  libcxx/include/typeinfo:344:11: note: in implicit copy constructor
  for 'std::bad_cast' first required here
      throw bad_cast();
	    ^

  Fix these by adding an explicitly defaulted copy constructor.

  The latter are like:

  libcxx/include/codecvt:105:37: warning: dynamic exception
  specifications are deprecated [-Wdeprecated-dynamic-exception-spec]
      virtual int do_encoding() const throw();
				      ^~~~~~~

  Fix these by using the _NOEXCEPT macro instead.

  Reviewers: EricWF, mclow.lists, ldionne, #libc

  Reviewed By: EricWF, #libc

  Subscribers: dexonsmith, libcxx-commits

  Tags: #libc

  Differential Revision: https://reviews.llvm.org/D76150

[PowerPC]: e500 target can't use lwsync, use msync instead

The e500 core has a silicon bug that triggers an illegal instruction
program trap on any sync other than msync. Other cores will typically
ignore illegal sync types, and the documentation even implies that
the 'illegal' bits are ignored.

Address this hardware deficiency by only using msync, like the PPC440.

Differential Revision:  https://reviews.llvm.org/D76614

[PowerPC]: Don't allow r0 as a target for LD_GOT_TPREL_L/32

Summary:
The linker is free to relax this (relocation R_PPC_GOT_TPREL16)
against R_PPC_TLS, if it sees fit (initial exec to local exec). If r0
is used, this can generate execution-invalid code (converts to 'addi
%rX, %r0, FOO, which translates in PPC-lingo to li %rX, FOO). Forbid
this instead.

This fixes static binaries using locales on FreeBSD/powerpc (tested
on FreeBSD/powerpcspe).

Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D76662

Make target features check work with ctor and dtor-

The problem was reported in PR45468, applying target features to an
always_inline constructor/destructor runs afoul of GlobalDecl
construction assert when checking for target-feature compatibility.

The core problem is fixed by using the version of the check that
takes a FunctionDecl rather than the GlobalDecl. However, while
writing the test, I discovered that source locations weren't properly
set for this check on ctors/dtors. This patch also fixes constructors
and CALLED destructors.

Unfortunately, it doesn't seem too possible to get a meaningful
source location for a 'cleanup' destructor, so those are still
'frontend' level errors unfortunately. A fixme was added to the test
to cover that situation.

[PowerPC] Change default for unaligned FP access for older subtargets

This is a fix for https://bugs.llvm.org/show_bug.cgi?id=40554

Some CPU's trap to the kernel on unaligned floating point access and
there are kernels that do not handle the interrupt. The program then
fails with a SIGBUS according to the PR. This just switches the
default for unaligned access to only allow it on recent server CPUs
that are known to allow this.

Differential revision: https://reviews.llvm.org/D71954

Fix bots after a9ad65a2b34f

In the last commit, I neglected to initialize the new subtarget
feature I added which caused failures on a few bots. This should fix
that.

Use FinishThunk to finish musttail thunks

FinishThunk, and the invariant of setting and then unsetting
CurCodeDecl, was added in 7f416cc42638 (2015). The invariant didn't
exist when I added this musttail codepath in ab2090d10765 (2014).
Recently in 28328c3771, I started using this codepath on non-Windows
platforms, and users reported problems during release testing
(PR44987).

The issue was already present for users of EH on i686-windows-msvc,
so I added a test for that case as well.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D76444

[PowerPC] Do not attempt to reuse load for 64-bit FP_TO_UINT without
FPCVT

We call the function that attempts to reuse the conversion without
checking whether the target matches the constraints that the callee
expects. This patch adds the check prior to the call.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=43976

Differential revision: https://reviews.llvm.org/D77564

[ARM] Only produce qadd8b under hasV6Ops

When compiling for a arm5te cpu from clang, the +dsp attribute is
set. This meant we could try and generate qadd8 instructions where we
would end up having no pattern. I've changed the condition here to be
hasV6Ops && hasDSP, which is what other parts of ARMISelLowering seem
to use for similar instructions.

Fixed PR45677.