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o Replace __riscv__ with __riscv

Description

o Replace riscv with riscv
o Replace
riscv64 with (riscv && riscv_xlen == 64)

This is required to support new GCC 7.1 compiler.
This is compatible with current GCC 6.1 compiler.

RISC-V is extensible ISA and the idea here is to have built-in define
per each extension, so together with __riscv we will have some subset
of these as well (depending on -march string passed to compiler):

riscv_compressed
riscv_atomic
riscv_mul
riscv_div
riscv_muldiv
riscv_fdiv
riscv_fsqrt
riscv_float_abi_soft
riscv_float_abi_single
riscv_float_abi_double
riscv_cmodel_medlow
riscv_cmodel_medany
riscv_cmodel_pic
riscv_xlen

Reviewed by: ngie
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D11901

Details

Provenance
brAuthored on
Reviewer
ngie
Differential Revision
D11901: RISC-V: support for GCC 7.1
Parents
rS322167: cxgbe(4): Add the T6 and T5 Unified Wire configuration files to the
Branches
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