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cad/verilator: create port

Description

cad/verilator: create port

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro

PR: 230761
Submitted by: Kevin Zheng <kevinz5000@gmail.com>

Details

Provenance
swillsAuthored on
Parents
rP490608: - Update to 2.12.2
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