Index: head/cad/Makefile =================================================================== --- head/cad/Makefile (revision 490608) +++ head/cad/Makefile (revision 490609) @@ -1,110 +1,111 @@ # $FreeBSD$ # COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += abc SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += basicdsp SUBDIR += brickutils SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += cascade SUBDIR += chipvault SUBDIR += cura-engine SUBDIR += dinotrace SUBDIR += dxf2fig SUBDIR += electric SUBDIR += electric-ng SUBDIR += elmerfem SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += ghdl SUBDIR += gmsh SUBDIR += gnucap SUBDIR += gplcver SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += k40-whisperer SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-library-footprints SUBDIR += kicad-library-footprints-devel SUBDIR += kicad-library-packages3d SUBDIR += kicad-library-packages3d-devel SUBDIR += kicad-library-symbols SUBDIR += kicad-library-symbols-devel SUBDIR += kicad-library-templates SUBDIR += kicad-library-templates-devel SUBDIR += klayout SUBDIR += layouteditor SUBDIR += ldraw SUBDIR += leocad SUBDIR += libopencad SUBDIR += librecad SUBDIR += libredwg SUBDIR += linux-eagle5 SUBDIR += linuxcnc-devel SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += meshlab SUBDIR += netgen SUBDIR += ngspice_rework SUBDIR += opencascade SUBDIR += openscad SUBDIR += openscad-devel SUBDIR += openvsp SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += pcb SUBDIR += pdnmesh SUBDIR += py-gdspy SUBDIR += py-lcapy SUBDIR += py-pycam SUBDIR += py-pyfda SUBDIR += python-gdsii SUBDIR += pythoncad SUBDIR += qcad SUBDIR += qelectrotech SUBDIR += qfsm SUBDIR += qmls SUBDIR += qucs SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += scotch SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += sumo SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += transcalc SUBDIR += varkon + SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += xcircuit SUBDIR += xtrkcad SUBDIR += z88 SUBDIR += zcad .include Index: head/cad/verilator/Makefile =================================================================== --- head/cad/verilator/Makefile (nonexistent) +++ head/cad/verilator/Makefile (revision 490609) @@ -0,0 +1,31 @@ +# $FreeBSD$ + +PORTNAME= verilator +PORTVERSION= 3.924 +CATEGORIES= cad +MASTER_SITES= https://www.veripool.org/ftp/ + +MAINTAINER= kevinz5000@gmail.com +COMMENT= Synthesizable Verilog to C++ compiler + +LICENSE= GPLv3 +LICENSE_FILE= ${WRKSRC}/COPYING + +BUILD_DEPENDS= flex:textproc/flex + +USES= bison gmake pathfix perl5 tar:tgz + +GNU_CONFIGURE= yes +CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}" + +post-patch: + ${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \ + ${WRKSRC}/Makefile.in + +post-build: + @${STRIP_CMD} ${WRKSRC}/bin/verilator_bin + +post-install: + ${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg + +.include Property changes on: head/cad/verilator/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/verilator/distinfo =================================================================== --- head/cad/verilator/distinfo (nonexistent) +++ head/cad/verilator/distinfo (revision 490609) @@ -0,0 +1,3 @@ +TIMESTAMP = 1534354040 +SHA256 (verilator-3.924.tgz) = 7dcb19711b8630ada59f0d3d7409faa9649e37bf4c53a0bbfcad32afb28b5975 +SIZE (verilator-3.924.tgz) = 2163952 Property changes on: head/cad/verilator/distinfo ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/verilator/pkg-descr =================================================================== --- head/cad/verilator/pkg-descr (nonexistent) +++ head/cad/verilator/pkg-descr (revision 490609) @@ -0,0 +1,8 @@ +Verilator is the fastest free Verilog HDL simulator, and beats most commercial +simulators. It compiles synthesizable Verilog (not test-bench code!), plus some +PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is +designed for large projects where fast simulation performance is of primary +concern, and is especially well suited to generate executable models of CPUs +for embedded software design teams. + +WWW: https://www.veripool.org/projects/verilator/wiki/Intro Property changes on: head/cad/verilator/pkg-descr ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/cad/verilator/pkg-plist =================================================================== --- head/cad/verilator/pkg-plist (nonexistent) +++ head/cad/verilator/pkg-plist (revision 490609) @@ -0,0 +1,54 @@ +bin/verilator +bin/verilator_bin +bin/verilator_coverage +bin/verilator_profcfunc +libdata/pkgconfig/verilator.pc +man/man1/verilator.1.gz +man/man1/verilator_coverage.1.gz +man/man1/verilator_profcfunc.1.gz +%%DATADIR%%/bin/verilator_includer +%%DATADIR%%/examples/hello_world_c/Makefile +%%DATADIR%%/examples/hello_world_c/sim_main.cpp +%%DATADIR%%/examples/hello_world_c/top.v +%%DATADIR%%/examples/hello_world_sc/Makefile +%%DATADIR%%/examples/hello_world_sc/sc_main.cpp +%%DATADIR%%/examples/hello_world_sc/top.v +%%DATADIR%%/examples/tracing_c/Makefile +%%DATADIR%%/examples/tracing_c/Makefile_obj +%%DATADIR%%/examples/tracing_c/input.vc +%%DATADIR%%/examples/tracing_c/sim_main.cpp +%%DATADIR%%/examples/tracing_c/sub.v +%%DATADIR%%/examples/tracing_c/top.v +%%DATADIR%%/examples/tracing_sc/Makefile +%%DATADIR%%/examples/tracing_sc/Makefile_obj +%%DATADIR%%/examples/tracing_sc/input.vc +%%DATADIR%%/examples/tracing_sc/sc_main.cpp +%%DATADIR%%/examples/tracing_sc/sub.v +%%DATADIR%%/examples/tracing_sc/top.v +%%DATADIR%%/include/verilated.cpp +%%DATADIR%%/include/verilated.h +%%DATADIR%%/include/verilated.mk +%%DATADIR%%/include/verilated.v +%%DATADIR%%/include/verilated_config.h +%%DATADIR%%/include/verilated_config.h.in +%%DATADIR%%/include/verilated_cov.cpp +%%DATADIR%%/include/verilated_cov.h +%%DATADIR%%/include/verilated_cov_key.h +%%DATADIR%%/include/verilated_dpi.cpp +%%DATADIR%%/include/verilated_dpi.h +%%DATADIR%%/include/verilated_heavy.h +%%DATADIR%%/include/verilated_imp.h +%%DATADIR%%/include/verilated_save.cpp +%%DATADIR%%/include/verilated_save.h +%%DATADIR%%/include/verilated_sc.h +%%DATADIR%%/include/verilated_sym_props.h +%%DATADIR%%/include/verilated_syms.h +%%DATADIR%%/include/verilated_vcd_c.cpp +%%DATADIR%%/include/verilated_vcd_c.h +%%DATADIR%%/include/verilated_vcd_sc.cpp +%%DATADIR%%/include/verilated_vcd_sc.h +%%DATADIR%%/include/verilated_vpi.cpp +%%DATADIR%%/include/verilated_vpi.h +%%DATADIR%%/include/verilatedos.h +%%DATADIR%%/include/vltstd/svdpi.h +%%DATADIR%%/include/vltstd/vpi_user.h Property changes on: head/cad/verilator/pkg-plist ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property