ARM GICv3: Add support for non-coherent and/or bus address range limited DMA.

Due to an implementation bug, the GICv3 and ITS master ports may be connected
to a non-coherent bus. The new DT resolves this issue by marking these ports
with the "dma-nocoherent" attribute. The older DT does not have this attribute,
so we must match the affected SoC.
Additionally, the RK356x family has GIC master ports on a 32-bit bus.
Therefore, we must limit the address range for all tables and command buffers
allocated for it. In this case, the DT does not have an attribute for this
case, so the quirk should only be applied by SoC matching.

MFC after: 4 weeks
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D47488