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Differential D3093

ARM64 TCR register update
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Authored by wma_semihalf.com on Jul 15 2015, 6:45 AM.
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andrew
emaste
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zbb
emaste
andrew
Commits
rS285626: Set-up proper TCR values for memory related to Translation Table Walking
Summary
This commit adds proper cache and shareability attributes to
the TCR registers.
Set memory attributes to Normal, outer and inner cacheable WBWA.
Set shareability to inner and outer shareable when SMP is enabled.

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rS FreeBSD src repository - subversion
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wma_semihalf.com updated this revision to Diff 6958.Jul 15 2015, 6:45 AM
wma_semihalf.com retitled this revision from to ARMv8 locore.S cleanup and TCR register update.
wma_semihalf.com updated this object.
wma_semihalf.com edited the test plan for this revision. (Show Details)
wma_semihalf.com added reviewers: zbb, emaste, andrew.
wma_semihalf.com set the repository for this revision to rS FreeBSD src repository - subversion.
wma_semihalf.com added a subscriber: freebsd-arm-list.
Herald added subscribers: emaste, andrew, imp. · View Herald TranscriptJul 15 2015, 6:45 AM
andrew edited edge metadata.Jul 15 2015, 8:59 AM

Why do you need to pass in the shareability attribute? It's needed for notmal memory, and ignored in device memory so we can add it unconditionally.

wma_semihalf.com updated this revision to Diff 6962.Jul 15 2015, 9:15 AM
wma_semihalf.com updated this object.
wma_semihalf.com edited edge metadata.

Agreed.

andrew added inline comments.Jul 15 2015, 10:41 AM
sys/arm64/arm64/locore.S
48–52

Is this still needed?

191

This looks to be unrelated to the rest of the change.

wma_semihalf.com added inline comments.Jul 15 2015, 10:47 AM
sys/arm64/arm64/locore.S
48–52

You're right, I'll remove it prior submitting.

191

It's the part of locore fixes described in the patch summary

  • secondary stack calculation is modified to provide stack_top = secondary_stacks + (cpu_id)*PAGE_SIZE*KSTACK_PAGES because on ARMv8 the stack grows into lower memory addresses

Please let me know if I should split this patch into two (include+stack and TCR reg) or leave as a one.

wma_semihalf.com updated this revision to Diff 7000.Jul 16 2015, 8:22 AM
wma_semihalf.com retitled this revision from ARMv8 locore.S cleanup and TCR register update to ARM64 TCR register update.
wma_semihalf.com updated this object.
wma_semihalf.com updated this revision to Diff 7005.Jul 16 2015, 8:32 AM
andrew accepted this revision.Jul 16 2015, 9:08 AM
andrew edited edge metadata.
This revision is now accepted and ready to land.Jul 16 2015, 9:08 AM
Closed by commit rS285626: Set-up proper TCR values for memory related to Translation Table Walking (authored by zbb). · Explain WhyJul 16 2015, 10:23 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents
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PathSize
sys/
arm64/
arm64/
69 lines
include/
22 lines

Diff 6958

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sys/arm64/arm64/locore.S

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sys/arm64/include/armreg.h

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