Add MIPS32/64 Rev2 intctl cp0 register definitions.
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Authored by landonf on Sep 9 2017, 9:56 PM.

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adrian

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rS323621: Add MIPS32/64 Rev2 CP0 intctl register definitions.

Summary

Add definitions for MIPS32/64 Rev 2 CPUs that provide an intctl register.

This can be used to:

Identify the CPU's internal timer interrupt #.
Identify the CPU's performance counter overflow interrupt #.
Control interrupt vector spacing.

Test Plan

Confirmed that sane values are returned on a Broadcom MIPS74K.

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No Test Coverage

Build Status

Buildable 11462
Build 11818: arc lint + arc unit

Event Timeline

landonf created this revision.Sep 9 2017, 9:56 PM

Harbormaster completed remote builds in B11462: Diff 32864.Sep 9 2017, 9:56 PM

lgtm

This revision is now accepted and ready to land.Sep 10 2017, 7:07 PM

Closed by commit rS323621: Add MIPS32/64 Rev2 CP0 intctl register definitions. (authored by landonf). · Explain WhySep 15 2017, 7:56 PM

This revision was automatically updated to reflect the committed changes.

Revision Contents
Changeset List

Path

Size

sys/

mips/

include/

cpufunc.h

9 lines

cpuregs.h

12 lines

Diff 32864

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sys/mips/include/cpufunc.h