jh7110_gpio: fdt_pinctrl interface
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Authored by mhorne on Thu, Sep 24, 4:35 PM.

Details

Reviewers

bscott_bunyatech.com.au

Group Reviewers

riscv

Summary

This provides GPIO programming/configuration at attach time based on the
device tree 'pinmux' descriptions.

Test Plan

Diff before after in configured pins, gpioctl -lv:

root@generic:~ # gpioctl -lv
 pin 00: 1       GPIO0<IN,PD>, caps:<IN,OUT,PU,PD>
 pin 01: 1       GPIO1<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 02: 1       GPIO2<IN>, caps:<IN,OUT,PU,PD>
@@ -10,13 +10,13 @@
 pin 08: 1       GPIO8<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 09: 1       GPIO9<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 10: 0       GPIO10<OUT,PU>, caps:<IN,OUT,PU,PD>
-pin 11: 0       GPIO11<IN,PU>, caps:<IN,OUT,PU,PD>
+pin 11: 1       GPIO11<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 12: 1       GPIO12<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 13: 1       GPIO13<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 14: 0       GPIO14<OUT>, caps:<IN,OUT,PU,PD>
 pin 15: 0       GPIO15<OUT>, caps:<IN,OUT,PU,PD>
-pin 16: 0       GPIO16<OUT>, caps:<IN,OUT,PU,PD>
-pin 17: 0       GPIO17<OUT>, caps:<IN,OUT,PU,PD>
+pin 16: 1       GPIO16<IN>, caps:<IN,OUT,PU,PD>
+pin 17: 1       GPIO17<IN>, caps:<IN,OUT,PU,PD>
 pin 18: 1       GPIO18<OUT,PU>, caps:<IN,OUT,PU,PD>
 pin 19: 1       GPIO19<IN>, caps:<IN,OUT,PU,PD>
 pin 20: 1       GPIO20<IN>, caps:<IN,OUT,PU,PD>
@@ -45,18 +45,18 @@
 pin 43: 1       GPIO43<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 44: 1       GPIO44<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 45: 1       GPIO45<OUT,PU>, caps:<IN,OUT,PU,PD>
-pin 46: 1       GPIO46<OUT,PU>, caps:<IN,OUT,PU,PD>
+pin 46: 0       GPIO46<IN>, caps:<IN,OUT,PU,PD>
 pin 47: 1       GPIO47<IN,PU>, caps:<IN,OUT,PU,PD>
-pin 48: 1       GPIO48<IN,PU>, caps:<IN,OUT,PU,PD>
-pin 49: 0       GPIO49<IN>, caps:<IN,OUT,PU,PD>
+pin 48: 0       GPIO48<OUT>, caps:<IN,OUT,PU,PD>
+pin 49: 0       GPIO49<OUT>, caps:<IN,OUT,PU,PD>
 pin 50: 0       GPIO50<IN>, caps:<IN,OUT,PU,PD>
 pin 51: 0       GPIO51<IN>, caps:<IN,OUT,PU,PD>
-pin 52: 1       GPIO52<IN,PU>, caps:<IN,OUT,PU,PD>
-pin 53: 0       GPIO53<IN>, caps:<IN,OUT,PU,PD>
+pin 52: 0       GPIO52<OUT>, caps:<IN,OUT,PU,PD>
+pin 53: 1       GPIO53<IN,PU>, caps:<IN,OUT,PU,PD>
 pin 54: 0       GPIO54<IN>, caps:<IN,OUT,PU,PD>
 pin 55: 0       GPIO55<IN>, caps:<IN,OUT,PU,PD>
 pin 56: 1       GPIO56<IN,PU>, caps:<IN,OUT,PU,PD>
-pin 57: 0       GPIO57<IN>, caps:<IN,OUT,PU,PD>
+pin 57: 1       GPIO57<IN>, caps:<IN,OUT,PU,PD>
 pin 58: 1       GPIO58<IN>, caps:<IN,OUT,PU,PD>
 pin 59: 0       GPIO59<IN>, caps:<IN,OUT,PU,PD>
 pin 60: 1       GPIO60<IN,PU>, caps:<IN,OUT,PU,PD>