To ensure there are no pending operations prior to putting the core in reset, you should spin here for 300ms (in 10us intervals) waiting for resetstatus to clear.

After this 10us delay, you should spin waiting for resetstatus to clear; the resetctrl read-back shouldn't be necessary.

I'd recommend a slightly different order of operations that leaves the clock enabled/stable during reset (not that there's any documentation for any of this stuff ...).

• Gate clock (SICF_FGC), but leave it enabled (SICF_CLOCK_EN).
• Take core out of reset by clearing resetctrl.
• Spin waiting for a read of resetctrl to return 0, retry up to ~10 times after first waiting up to 300us (in 10us intervals) for resetstatus to clear (for total possible delay of 3000us)
• Disable clock gating (clear SICF_FGC).

These bcma-specific register offsets and bitflags are defined in bcma_dmp.h; can you switch to using those?

The bhnd_core.h header is shared with siba(4), which has its own register offsets/layout, but uses most of the same flags (including core-specific flags).

BCMA Offsets:

• BHND_CF ->BCMA_DMP_IOCTRL (0x408)
• BHND_SF -> BCMA_DMP_IOSTATUS (0x500)
• BHND_RESET_CF -> BCMA_DMP_RESETCTRL (0x800)
• BHND_RESET_SF -> BCMA_DMP_RESETSTATUS (0x804)

BCMA Flags:

• BHND_RESET_CF_ENABLE -> BCMA_DMP_RC_RESET (0x0001)