rc: Set var_run_enable to enable by default
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Authored by manu on Feb 27 2024, 5:35 PM.

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rGac658a7c760d: rc: Set var_run_enable to enable by default
rG72b045386dd3: rc: Set var_run_enable to enable by default

Summary

This will load/save the /var/run directories at boot/shutdown if
and only if /var/run/ is a tmpfs mount so it is a win for tmpfs
users and a no-op for everyone else.

Sponsored by: Beckhoff Automation GmbH & Co. KG

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rG FreeBSD src repository

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Tests Not Applicable

Event Timeline

manu created this revision.Feb 27 2024, 5:35 PM

Herald added a subscriber: imp. · View Herald TranscriptFeb 27 2024, 5:35 PM

Harbormaster completed remote builds in B56268: Diff 135074.Feb 27 2024, 5:35 PM

manu requested review of this revision.Feb 27 2024, 5:35 PM

bapt accepted this revision.Feb 27 2024, 6:29 PM

This revision is now accepted and ready to land.Feb 27 2024, 6:29 PM

Closed by commit rG72b045386dd3: rc: Set var_run_enable to enable by default (authored by manu). · Explain WhyFeb 28 2024, 7:18 AM

This revision was automatically updated to reflect the committed changes.

manu added a commit: rG72b045386dd3: rc: Set var_run_enable to enable by default.

manu added a commit: rGac658a7c760d: rc: Set var_run_enable to enable by default.Jun 4 2024, 11:39 AM

Revision Contents
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Path

Size

libexec/

rc/

rc.conf

4 lines

rc.d/

var_run

5 lines

Diff 135149

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libexec/rc/rc.conf

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines	#define __PMC_CPUS() \
__PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \		__PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \
__PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \		__PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
__PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \		__PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
__PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \		__PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \
__PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \		__PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \
__PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \		__PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \
__PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \		__PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \
__PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \		__PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \
		__PMC_CPU(INTEL_KABYLAKE, 0x9A, "Intel Kabylake") \
__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \		__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \		__PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \		__PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
__PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \		__PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \
__PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \		__PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
__PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \		__PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \
__PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \		__PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
__PMC_CPU(GENERIC, 0x400, "Generic") \		__PMC_CPU(GENERIC, 0x400, "Generic") \
Show All 34 Lines	#define __PMC_CLASSES() \
__PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \		__PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \
__PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \		__PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \
__PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \		__PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \
__PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \		__PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \
__PMC_CLASS(SOFT, 0x0F, "Software events") \		__PMC_CLASS(SOFT, 0x0F, "Software events") \
__PMC_CLASS(ARMV7, 0x10, "ARMv7") \		__PMC_CLASS(ARMV7, 0x10, "ARMv7") \
__PMC_CLASS(ARMV8, 0x11, "ARMv8") \		__PMC_CLASS(ARMV8, 0x11, "ARMv8") \
__PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \		__PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \
__PMC_CLASS(E500, 0x13, "Freescale e500 class")		__PMC_CLASS(E500, 0x13, "Freescale e500 class") \
		__PMC_CLASS(PT, 0x14, "Intel PT") \
		__PMC_CLASS(CORESIGHT, 0x15, "ARM Coresight")

enum pmc_class {		enum pmc_class {
#undef __PMC_CLASS		#undef __PMC_CLASS
#define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V,		#define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V,
__PMC_CLASSES()		__PMC_CLASSES()
};		};

#define PMC_CLASS_FIRST PMC_CLASS_TSC		#define PMC_CLASS_FIRST PMC_CLASS_TSC
#define PMC_CLASS_LAST PMC_CLASS_E500		#define PMC_CLASS_LAST PMC_CLASS_CORESIGHT

/*		/*
* A PMC can be in the following states:		* A PMC can be in the following states:
*		*
* Hardware states:		* Hardware states:
* DISABLED -- administratively prohibited from being used.		* DISABLED -- administratively prohibited from being used.
* FREE -- HW available for use		* FREE -- HW available for use
* Software states:		* Software states:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
* The system-wide "global" modes keep the PMCs running all the time		* The system-wide "global" modes keep the PMCs running all the time
* and are used to measure the behaviour of the whole system.		* and are used to measure the behaviour of the whole system.
*/		*/

#define __PMC_MODES() \		#define __PMC_MODES() \
__PMC_MODE(SS, 0) \		__PMC_MODE(SS, 0) \
__PMC_MODE(SC, 1) \		__PMC_MODE(SC, 1) \
__PMC_MODE(TS, 2) \		__PMC_MODE(TS, 2) \
__PMC_MODE(TC, 3)		__PMC_MODE(TC, 3) \
		__PMC_MODE(ST, 4) \
		__PMC_MODE(TT, 5)

enum pmc_mode {		enum pmc_mode {
#undef __PMC_MODE		#undef __PMC_MODE
#define __PMC_MODE(M,N) PMC_MODE_##M = N,		#define __PMC_MODE(M,N) PMC_MODE_##M = N,
__PMC_MODES()		__PMC_MODES()
};		};

#define PMC_MODE_FIRST PMC_MODE_SS		#define PMC_MODE_FIRST PMC_MODE_SS
#define PMC_MODE_LAST PMC_MODE_TC		#define PMC_MODE_LAST PMC_MODE_TC

#define PMC_IS_COUNTING_MODE(mode) \		#define PMC_IS_COUNTING_MODE(mode) \
((mode) == PMC_MODE_SC \|\| (mode) == PMC_MODE_TC)		((mode) == PMC_MODE_SC \|\| (mode) == PMC_MODE_TC)
#define PMC_IS_SYSTEM_MODE(mode) \		#define PMC_IS_SYSTEM_MODE(mode) \
((mode) == PMC_MODE_SS \|\| (mode) == PMC_MODE_SC)		((mode) == PMC_MODE_SS \|\| (mode) == PMC_MODE_SC \|\| (mode) == PMC_MODE_ST)
#define PMC_IS_SAMPLING_MODE(mode) \		#define PMC_IS_SAMPLING_MODE(mode) \
((mode) == PMC_MODE_SS \|\| (mode) == PMC_MODE_TS)		((mode) == PMC_MODE_SS \|\| (mode) == PMC_MODE_TS)
#define PMC_IS_VIRTUAL_MODE(mode) \		#define PMC_IS_VIRTUAL_MODE(mode) \
((mode) == PMC_MODE_TS \|\| (mode) == PMC_MODE_TC)		((mode) == PMC_MODE_TS \|\| (mode) == PMC_MODE_TC \|\| (mode) == PMC_MODE_TT)

/*		/*
* PMC row disposition		* PMC row disposition
*/		*/

#define __PMC_DISPOSITIONS(N) \		#define __PMC_DISPOSITIONS(N) \
__PMC_DISP(STANDALONE) /* global/disabled counters */ \		__PMC_DISP(STANDALONE) /* global/disabled counters */ \
__PMC_DISP(FREE) /* free/available */ \		__PMC_DISP(FREE) /* free/available */ \
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines	#define __PMC_OPS() \
__PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \		__PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
__PMC_OP(PMCRELEASE, "Release a PMC") \		__PMC_OP(PMCRELEASE, "Release a PMC") \
__PMC_OP(PMCRW, "Read/Set a PMC") \		__PMC_OP(PMCRW, "Read/Set a PMC") \
__PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \		__PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
__PMC_OP(PMCSTART, "Start a PMC") \		__PMC_OP(PMCSTART, "Start a PMC") \
__PMC_OP(PMCSTOP, "Stop a PMC") \		__PMC_OP(PMCSTOP, "Stop a PMC") \
__PMC_OP(WRITELOG, "Write a cookie to the log file") \		__PMC_OP(WRITELOG, "Write a cookie to the log file") \
__PMC_OP(CLOSELOG, "Close log file") \		__PMC_OP(CLOSELOG, "Close log file") \
__PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")		__PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") \
		__PMC_OP(LOG_KERNEL_MAP, "Log kernel mappings") \
		__PMC_OP(THREAD_UNSUSPEND, "Thread unsuspend") \
		__PMC_OP(TRACE_READ, "Read trace buffer pointer") \
		__PMC_OP(TRACE_CONFIG, "Setup trace IP ranges")


enum pmc_ops {		enum pmc_ops {
#undef __PMC_OP		#undef __PMC_OP
#define __PMC_OP(N, D) PMC_OP_##N,		#define __PMC_OP(N, D) PMC_OP_##N,
__PMC_OPS()		__PMC_OPS()
};		};

▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines


struct pmc_op_pmcrw {		struct pmc_op_pmcrw {
uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/		uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
pmc_id_t pm_pmcid; /* pmc id */		pmc_id_t pm_pmcid; /* pmc id */
pmc_value_t pm_value; /* new&returned value */		pmc_value_t pm_value; /* new&returned value */
};		};


/*		/*
* OP GETPMCINFO		* OP GETPMCINFO
*		*
* retrieve PMC state for a named CPU. The caller is expected to		* retrieve PMC state for a named CPU. The caller is expected to
* allocate 'npmc' * 'struct pmc_info' bytes of space for the return		* allocate 'npmc' * 'struct pmc_info' bytes of space for the return
* values.		* values.
*/		*/

Show All 9 Lines	struct pmc_info {
pmc_value_t pm_reloadcount; /* sampling counters only */		pmc_value_t pm_reloadcount; /* sampling counters only */
};		};

struct pmc_op_getpmcinfo {		struct pmc_op_getpmcinfo {
int32_t pm_cpu; /* 0 <= cpu < mp_maxid */		int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */		struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
};		};

		/*
		* OP PROC_UNSUSPEND
		*
		* Unsuspend all threads of proc.
		*/

		struct pmc_op_proc_unsuspend {
		pmc_id_t pm_pmcid;
		pid_t pm_pid;
		};

/*		/*
		* OP TRACE_CONFIG
		*/

		#define PMC_FILTER_MAX_IP_RANGES 4

		struct pmc_op_trace_config {
		pmc_id_t pm_pmcid;
		uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
		uint64_t ranges[2 * PMC_FILTER_MAX_IP_RANGES];
		uint32_t nranges;
		};

		/*
		* OP TRACE_READ
		*/

		struct pmc_op_trace_read {
		pmc_id_t pm_pmcid;
		uint32_t pm_cpu;
		pmc_value_t pm_cycle; /* returned value */
		pmc_value_t pm_offset; /* returned value */
		};

		/*
* OP GETCPUINFO		* OP GETCPUINFO
*		*
* Retrieve system CPU information.		* Retrieve system CPU information.
*/		*/


struct pmc_classinfo {		struct pmc_classinfo {
enum pmc_class pm_class; /* class id */		enum pmc_class pm_class; /* class id */
uint32_t pm_caps; /* counter capabilities */		uint32_t pm_caps; /* counter capabilities */
uint32_t pm_width; /* width of the PMC */		uint32_t pm_width; /* width of the PMC */
uint32_t pm_num; /* number of PMCs in class */		uint32_t pm_num; /* number of PMCs in class */
};		};

struct pmc_op_getcpuinfo {		struct pmc_op_getcpuinfo {
▲ Show 20 Lines • Show All 468 Lines • ▼ Show 20 Lines	struct pmc_classdep {
int pcd_ri; /* row index of the first PMC in class */		int pcd_ri; /* row index of the first PMC in class */
int pcd_width; /* width of the PMC */		int pcd_width; /* width of the PMC */

/* configuring/reading/writing the hardware PMCs */		/* configuring/reading/writing the hardware PMCs */
int (pcd_config_pmc)(int _cpu, int _ri, struct pmc _pm);		int (pcd_config_pmc)(int _cpu, int _ri, struct pmc _pm);
int (pcd_get_config)(int _cpu, int _ri, struct pmc *_ppm);		int (pcd_get_config)(int _cpu, int _ri, struct pmc *_ppm);
int (pcd_read_pmc)(int _cpu, int _ri, pmc_value_t _value);		int (pcd_read_pmc)(int _cpu, int _ri, pmc_value_t _value);
int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);		int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);

		/* trace */
		int (pcd_read_trace)(int _cpu, int _ri, struct pmc _pm,
		pmc_value_t _cycle, pmc_value_t _offset);
		int (pcd_trace_config)(int _cpu, int _ri, struct pmc _pm,
		uint64_t *ranges, uint32_t nranges);

/* pmc allocation/release */		/* pmc allocation/release */
int (pcd_allocate_pmc)(int _cpu, int _ri, struct pmc _t,		int (pcd_allocate_pmc)(int _cpu, int _ri, struct pmc _t,
const struct pmc_op_pmcallocate *_a);		const struct pmc_op_pmcallocate *_a);
int (pcd_release_pmc)(int _cpu, int _ri, struct pmc _pm);		int (pcd_release_pmc)(int _cpu, int _ri, struct pmc _pm);

/* starting and stopping PMCs */		/* starting and stopping PMCs */
int (*pcd_start_pmc)(int _cpu, int _ri);		int (*pcd_start_pmc)(int _cpu, int _ri);
Show All 12 Lines
};		};

/*		/*
* struct pmc_mdep		* struct pmc_mdep
*		*
* Machine dependent bits needed per CPU type.		* Machine dependent bits needed per CPU type.
*/		*/

struct pmc_mdep {		struct pmc_mdep {
uint32_t pmd_cputype; /* from enum pmc_cputype */		uint32_t pmd_cputype; /* from enum pmc_cputype */
uint32_t pmd_npmc; /* number of PMCs per CPU */		uint32_t pmd_npmc; /* number of PMCs per CPU */
uint32_t pmd_nclass; /* number of PMC classes present */		uint32_t pmd_nclass; /* number of PMC classes present */

/*		/*
* Machine dependent methods.		* Machine dependent methods.
*/		*/

▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines