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Differential D38970

arch.7: Drop most mentions of MIPS.
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Authored by jhb on Mar 8 2023, 1:03 AM.
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rG6dcd6d199f86: arch.7: Drop most mentions of MIPS.
Summary

Only keep MIPS in the list of deprecated architectures.

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rG FreeBSD src repository
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Event Timeline

jhb requested review of this revision.Mar 8 2023, 1:03 AM
jhb created this revision.
Harbormaster completed remote builds in B50217: Diff 118510.Mar 8 2023, 1:03 AM
jhb added a reviewer: emaste.Mar 8 2023, 4:59 PM
emaste accepted this revision.Mar 8 2023, 5:16 PM
This revision is now accepted and ready to land.Mar 8 2023, 5:16 PM
Closed by commit rG6dcd6d199f86: arch.7: Drop most mentions of MIPS. (authored by jhb). · Explain WhyMar 8 2023, 11:13 PM
This revision was automatically updated to reflect the committed changes.
jhb added a commit: rG6dcd6d199f86: arch.7: Drop most mentions of MIPS..

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share/
man/
man7/
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share/man/man7/arch.7

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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE. .\" SUCH DAMAGE.
.\" .\"
.\" $FreeBSD$ .\" $FreeBSD$
.\" .\"
.Dd September 15, 2022 .Dd March 8, 2023
.Dt ARCH 7 .Dt ARCH 7
.Os .Os
.Sh NAME .Sh NAME
.Nm arch .Nm arch
.Nd Architecture-specific details .Nd Architecture-specific details
.Sh DESCRIPTION .Sh DESCRIPTION
Differences between CPU architectures and platforms supported by Differences between CPU architectures and platforms supported by
.Fx . .Fx .
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.Dq legacy .Dq legacy
.Dv ILP32 .Dv ILP32
environment, which was the historical 32-bit predecessor for 64-bit evolution. environment, which was the historical 32-bit predecessor for 64-bit evolution.
Examples are: Examples are:
.Bl -column -offset indent "powerpc64" "ILP32 counterpart" .Bl -column -offset indent "powerpc64" "ILP32 counterpart"
.It Sy LP64 Ta Sy ILP32 counterpart .It Sy LP64 Ta Sy ILP32 counterpart
.It Dv amd64 Ta Dv i386 .It Dv amd64 Ta Dv i386
.It Dv powerpc64 Ta Dv powerpc .It Dv powerpc64 Ta Dv powerpc
.It Dv mips64* Ta Dv mips*
.It Dv aarch64 Ta Dv armv6/armv7 .It Dv aarch64 Ta Dv armv6/armv7
.El .El
.Pp .Pp
.Dv aarch64 .Dv aarch64
will support execution of will support execution of
.Dv armv6 .Dv armv6
or or
.Dv armv7 .Dv armv7
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Machine-dependent type sizes: Machine-dependent type sizes:
.Bl -column -offset indent "Architecture" "void *" "long double" "time_t" .Bl -column -offset indent "Architecture" "void *" "long double" "time_t"
.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t .It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
.It aarch64 Ta 8 Ta 16 Ta 8 .It aarch64 Ta 8 Ta 16 Ta 8
.It amd64 Ta 8 Ta 16 Ta 8 .It amd64 Ta 8 Ta 16 Ta 8
.It armv6 Ta 4 Ta 8 Ta 8 .It armv6 Ta 4 Ta 8 Ta 8
.It armv7 Ta 4 Ta 8 Ta 8 .It armv7 Ta 4 Ta 8 Ta 8
.It i386 Ta 4 Ta 12 Ta 4 .It i386 Ta 4 Ta 12 Ta 4
.It mips Ta 4 Ta 8 Ta 8
.It mipsel Ta 4 Ta 8 Ta 8
.It mipselhf Ta 4 Ta 8 Ta 8
.It mipshf Ta 4 Ta 8 Ta 8
.It mipsn32 Ta 4 Ta 8 Ta 8
.It mips64 Ta 8 Ta 8 Ta 8
.It mips64el Ta 8 Ta 8 Ta 8
.It mips64elhf Ta 8 Ta 8 Ta 8
.It mips64hf Ta 8 Ta 8 Ta 8
.It powerpc Ta 4 Ta 8 Ta 8 .It powerpc Ta 4 Ta 8 Ta 8
.It powerpcspe Ta 4 Ta 8 Ta 8 .It powerpcspe Ta 4 Ta 8 Ta 8
.It powerpc64 Ta 8 Ta 8 Ta 8 .It powerpc64 Ta 8 Ta 8 Ta 8
.It powerpc64le Ta 8 Ta 8 Ta 8 .It powerpc64le Ta 8 Ta 8 Ta 8
.It riscv64 Ta 8 Ta 16 Ta 8 .It riscv64 Ta 8 Ta 16 Ta 8
.It riscv64sf Ta 8 Ta 16 Ta 8 .It riscv64sf Ta 8 Ta 16 Ta 8
.El .El
.Pp .Pp
.Sy time_t .Sy time_t
is 8 bytes on all supported architectures except i386. is 8 bytes on all supported architectures except i386.
.Ss Endianness and Char Signedness .Ss Endianness and Char Signedness
.Bl -column -offset indent "Architecture" "Endianness" "char Signedness" .Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness .It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
.It aarch64 Ta little Ta unsigned .It aarch64 Ta little Ta unsigned
.It amd64 Ta little Ta signed .It amd64 Ta little Ta signed
.It armv6 Ta little Ta unsigned .It armv6 Ta little Ta unsigned
.It armv7 Ta little Ta unsigned .It armv7 Ta little Ta unsigned
.It i386 Ta little Ta signed .It i386 Ta little Ta signed
.It mips Ta big Ta signed
.It mipsel Ta little Ta signed
.It mipselhf Ta little Ta signed
.It mipshf Ta big Ta signed
.It mipsn32 Ta big Ta signed
.It mips64 Ta big Ta signed
.It mips64el Ta little Ta signed
.It mips64elhf Ta little Ta signed
.It mips64hf Ta big Ta signed
.It powerpc Ta big Ta unsigned .It powerpc Ta big Ta unsigned
.It powerpcspe Ta big Ta unsigned .It powerpcspe Ta big Ta unsigned
.It powerpc64 Ta big Ta unsigned .It powerpc64 Ta big Ta unsigned
.It powerpc64le Ta little Ta unsigned .It powerpc64le Ta little Ta unsigned
.It riscv64 Ta little Ta signed .It riscv64 Ta little Ta signed
.It riscv64sf Ta little Ta signed .It riscv64sf Ta little Ta signed
.El .El
.Ss Page Size .Ss Page Size
.Bl -column -offset indent "Architecture" "Page Sizes" .Bl -column -offset indent "Architecture" "Page Sizes"
.It Sy Architecture Ta Sy Page Sizes .It Sy Architecture Ta Sy Page Sizes
.It aarch64 Ta 4K, 2M, 1G .It aarch64 Ta 4K, 2M, 1G
.It amd64 Ta 4K, 2M, 1G .It amd64 Ta 4K, 2M, 1G
.It armv6 Ta 4K, 1M .It armv6 Ta 4K, 1M
.It armv7 Ta 4K, 1M .It armv7 Ta 4K, 1M
.It i386 Ta 4K, 2M (PAE), 4M .It i386 Ta 4K, 2M (PAE), 4M
.It mips Ta 4K
.It mipsel Ta 4K
.It mipselhf Ta 4K
.It mipshf Ta 4K
.It mipsn32 Ta 4K
.It mips64 Ta 4K
.It mips64el Ta 4K
.It mips64elhf Ta 4K
.It mips64hf Ta 4K
.It powerpc Ta 4K .It powerpc Ta 4K
.It powerpcspe Ta 4K .It powerpcspe Ta 4K
.It powerpc64 Ta 4K .It powerpc64 Ta 4K
.It powerpc64le Ta 4K .It powerpc64le Ta 4K
.It riscv64 Ta 4K, 2M, 1G .It riscv64 Ta 4K, 2M, 1G
.It riscv64sf Ta 4K, 2M, 1G .It riscv64sf Ta 4K, 2M, 1G
.El .El
.Ss Floating Point .Ss Floating Point
.Bl -column -offset indent "Architecture" "float, double" "long double" .Bl -column -offset indent "Architecture" "float, double" "long double"
.It Sy Architecture Ta Sy float, double Ta Sy long double .It Sy Architecture Ta Sy float, double Ta Sy long double
.It aarch64 Ta hard Ta soft, quad precision .It aarch64 Ta hard Ta soft, quad precision
.It amd64 Ta hard Ta hard, 80 bit .It amd64 Ta hard Ta hard, 80 bit
.It armv6 Ta hard Ta hard, double precision .It armv6 Ta hard Ta hard, double precision
.It armv7 Ta hard Ta hard, double precision .It armv7 Ta hard Ta hard, double precision
.It i386 Ta hard Ta hard, 80 bit .It i386 Ta hard Ta hard, 80 bit
.It mips Ta soft Ta identical to double
.It mipsel Ta soft Ta identical to double
.It mipselhf Ta hard Ta identical to double
.It mipshf Ta hard Ta identical to double
.It mipsn32 Ta soft Ta identical to double
.It mips64 Ta soft Ta identical to double
.It mips64el Ta soft Ta identical to double
.It mips64elhf Ta hard Ta identical to double
.It mips64hf Ta hard Ta identical to double
.It powerpc Ta hard Ta hard, double precision .It powerpc Ta hard Ta hard, double precision
.It powerpcspe Ta hard Ta hard, double precision .It powerpcspe Ta hard Ta hard, double precision
.It powerpc64 Ta hard Ta hard, double precision .It powerpc64 Ta hard Ta hard, double precision
.It powerpc64le Ta hard Ta hard, double precision .It powerpc64le Ta hard Ta hard, double precision
.It riscv64 Ta hard Ta hard, quad precision .It riscv64 Ta hard Ta hard, quad precision
.It riscv64sf Ta soft Ta soft, quad precision .It riscv64sf Ta soft Ta soft, quad precision
.El .El
.Ss Default Tool Chain .Ss Default Tool Chain
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when referring to the kernel, interfaces dependent on a specific type of kernel when referring to the kernel, interfaces dependent on a specific type of kernel
or similar things like boot sequences. or similar things like boot sequences.
.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH" .Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH .It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
.It arm64 Ta aarch64 Ta aarch64 .It arm64 Ta aarch64 Ta aarch64
.It amd64 Ta amd64 Ta amd64 .It amd64 Ta amd64 Ta amd64
.It arm Ta arm Ta armv6, armv7 .It arm Ta arm Ta armv6, armv7
.It i386 Ta i386 Ta i386 .It i386 Ta i386 Ta i386
.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le .It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le
.It riscv Ta riscv Ta riscv64, riscv64sf .It riscv Ta riscv Ta riscv64, riscv64sf
.El .El
.Ss Predefined Macros .Ss Predefined Macros
The compiler provides a number of predefined macros. The compiler provides a number of predefined macros.
Some of these provide architecture-specific details and are explained below. Some of these provide architecture-specific details and are explained below.
Other macros, including those required by the language standard, are not Other macros, including those required by the language standard, are not
included here. included here.
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Architecture-specific macros: Architecture-specific macros:
.Bl -column -offset indent "Architecture" "Predefined macros" .Bl -column -offset indent "Architecture" "Predefined macros"
.It Sy Architecture Ta Sy Predefined macros .It Sy Architecture Ta Sy Predefined macros
.It aarch64 Ta Dv __aarch64__ .It aarch64 Ta Dv __aarch64__
.It amd64 Ta Dv __amd64__ , Dv __x86_64__ .It amd64 Ta Dv __amd64__ , Dv __x86_64__
.It armv6 Ta Dv __arm__ , Dv __ARM_ARCH >= 6 .It armv6 Ta Dv __arm__ , Dv __ARM_ARCH >= 6
.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7 .It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7
.It i386 Ta Dv __i386__ .It i386 Ta Dv __i386__
.It mips Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32
.It mipsel Ta Dv __mips__ , Dv __mips_o32
.It mipselhf Ta Dv __mips__ , Dv __mips_o32
.It mipshf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_o32
.It mipsn32 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n32
.It mips64 Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64
.It mips64el Ta Dv __mips__ , Dv __mips_n64
.It mips64elhf Ta Dv __mips__ , Dv __mips_n64
.It mips64hf Ta Dv __mips__ , Dv __MIPSEB__ , Dv __mips_n64
.It powerpc Ta Dv __powerpc__ .It powerpc Ta Dv __powerpc__
.It powerpcspe Ta Dv __powerpc__ , Dv __SPE__ .It powerpcspe Ta Dv __powerpc__ , Dv __SPE__
.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__ .It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__
.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__ .It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__
.It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64 .It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64
.It riscv64sf Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __riscv_float_abi_soft .It riscv64sf Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __riscv_float_abi_soft
.El .El
.Pp .Pp
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output. output.
It defines the CPU instruction family supported. It defines the CPU instruction family supported.
It may also encode a variation in the byte ordering of multi-byte It may also encode a variation in the byte ordering of multi-byte
integers (endian). integers (endian).
It may also encode a variation in the size of the integer or pointer. It may also encode a variation in the size of the integer or pointer.
It may also encode a ISA revision. It may also encode a ISA revision.
It may also encode hard versus soft floating point ABI and usage. It may also encode hard versus soft floating point ABI and usage.
It may also encode a variant ABI when the other factors do not It may also encode a variant ABI when the other factors do not
uniquely define the ABI (e.g., MIPS' n32 ABI). uniquely define the ABI.
It, along with It, along with
.Dv MACHINE , .Dv MACHINE ,
defines the ABI used by the system. defines the ABI used by the system.
For example, the MIPS CPU processor family supports 9 different
combinations encoding pointer size, endian and hard versus soft float (for
8 combinations) as well as N32 (which only ever had one variation of
all these).
Generally, the plain CPU name specifies the most common (or at least Generally, the plain CPU name specifies the most common (or at least
first) variant of the CPU. first) variant of the CPU.
This is why mips and mips64 imply 'big endian' while 'armv6' and 'armv7' This is why powerpc and powerpc64 imply 'big endian' while 'armv6' and 'armv7'
imply little endian. imply little endian.
If we ever were to support the so-called x32 ABI (using 32-bit If we ever were to support the so-called x32 ABI (using 32-bit
pointers on the amd64 architecture), it would most likely be encoded pointers on the amd64 architecture), it would most likely be encoded
as amd64-x32. as amd64-x32.
It is unfortunate that amd64 specifies the 64-bit evolution of the x86 It is unfortunate that amd64 specifies the 64-bit evolution of the x86
platform (it matches the 'first rule') as everybody else uses x86_64. platform (it matches the 'first rule') as everybody else uses x86_64.
There is no standard name for the processor: each OS selects its own There is no standard name for the processor: each OS selects its own
conventions. conventions.
.It Dv MACHINE_CPUARCH .It Dv MACHINE_CPUARCH
Represents the source location for a given Represents the source location for a given
.Dv MACHINE_ARCH . .Dv MACHINE_ARCH .
It is generally the common prefix for all the MACHINE_ARCH that It is generally the common prefix for all the MACHINE_ARCH that
share the same implementation, though 'riscv' breaks this rule. share the same implementation, though 'riscv' breaks this rule.
For example,
.Dv MACHINE_CPUARCH
is defined to be mips for all the flavors of mips that we support
since we support them all with a shared set of sources.
While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86 While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
for them. for them.
The The
.Fx .Fx
source base supports amd64 and i386 with two source base supports amd64 and i386 with two
distinct source bases living in subdirectories named amd64 and i386 distinct source bases living in subdirectories named amd64 and i386
(though behind the scenes there's some sharing that fits into this (though behind the scenes there's some sharing that fits into this
framework). framework).
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