mpi3mr: Reduce diagnostic register unlock polling delay to 200us

[chandrakanth.patil_broadcom.com]

Summary

When issuing a controller reset, the driver writes an unlock magic
sequence to access the host diagnostic register, previously followed
by a fixed 1ms (1000us) delay before checking if write access was
enabled.

Because the hardware typically enables write access much faster, the
fixed 1ms wait added unnecessary delay to reset operations. Poll the
diagnostic register up to 5 times at 200us intervals, breaking out
immediately once DIAG_WRITE_ENABLE is set. This preserves the 1ms total
retry window while significantly speeding up reset recovery.

Test Plan

• Clean build with WERROR=-Werror across FreeBSD 16, 15, and 14 with INVARIANTS/WITNESS enabled; git bisect verified.
• Tested soft reset and online controller resets (OCR) on SAS4116/SAS5116 controllers under active I/O.
• Verified faster diagnostic register unlocking with immediate breakout upon write enablement.

[imp]

sys/dev/mpi3mr/mpi3mr.c

6280

So this is fine. But is there any reason

[imp]

sys/dev/mpi3mr/mpi3mr.c

6280

I was going to delete this comment, but botched that.

The full question is 'why 200us? Why not to 50 times at 20us?'