- Modified pciconf to print EA capability structure
- Added register description to pcireg.h
OUTPUT:
root# pciconf -lc pci2:1:0:0
vnicpf0@pci2:1:0:0: class=0x020000 card=0xa11e177d chip=0xa01e177d rev=0x08 hdr=0x00
cap 10[40] = PCI-Express 2 endpoint max data 128(128) link x0(x0)
cap 11[80] = MSI-X supports 10 messages, enabled
Table in map 0x20[0x0], PBA in map 0x20[0xf0000]
cap 14[98] = PCI Enhanced Allocation (4 entries)
[0] BAR0, Enabled, Read-only, base [0x843000000000], size [0x40000000]
Primary properties [0x0] (Non-Prefetchable Memory)
Secondary properties [0xff] (Unavailable)
[4] BAR4, Enabled, Read-only, base [0x843060000000], size [0x100000]
Primary properties [0x0] (Non-Prefetchable Memory)
Secondary properties [0xff] (Unavailable)
[9] VFBAR0, Enabled, Read-only, base [0x8430a0000000], size [0x200000]
Primary properties [0x4] (VF Non-Prefetchable Memory)
Secondary properties [0xff] (Unavailable)
[13] VFBAR4, Enabled, Read-only, base [0x8430e0000000], size [0x200000]
Primary properties [0x4] (VF Non-Prefetchable Memory)
Secondary properties [0xff] (Unavailable)
ecap 000e[100] = ARI 1
ecap 000b[108] = Vendor 1 ID 160
ecap 0010[180] = SR-IOV 1 IOV enabled, Memory Space enabled, ARI enabled
128 VFs configured out of 128 supported
First VF RID Offset 0x0001, VF RID Stride 0x0001
VF Device ID 0xa034
Page Sizes: 4096 (enabled), 8192 (enabled), 65536 (enabled), 262144 (enabled), 1048576 (enabled), 4194304