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urtwn: add bits for R92C_HWSEQ_CTRL and R92C_TXPAUSE registers
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Authored by avos on Jan 3 2016, 10:45 PM.
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rS FreeBSD src repository - subversion
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avos retitled this revision from to urtwn: add bits for R92C_HWSEQ_CTRL and R92C_TXPAUSE registers.
avos updated this object.
avos edited the test plan for this revision. (Show Details)
avos added reviewers: adrian, kevlo.
avos set the repository for this revision to rS FreeBSD src repository - subversion.
kevlo edited edge metadata.
This revision is now accepted and ready to land.Jan 4 2016, 2:38 AM
adrian edited edge metadata.

looks good to me!

This revision was automatically updated to reflect the committed changes.