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Fix possible coherency issues between PEs related to I-cache
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Authored by wma_semihalf.com on Jul 16 2015, 5:09 AM.
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Details

Summary
Basing on B.2.3.4:
Synchronization and coherency issues between data and
instruction accesses.

To ensure that modified instructions are visible to all PEs
in a shareability domain one need to perform following sequence:
1. Clean D-cache
2. Ensure the visibility of data cleaned from cache
3. Invalidate I-cache
4. Ensure completion
5. In SMP system PE must issue isb to ensure execution of the
   modified instructions

Diff Detail

Repository
rS FreeBSD src repository - subversion
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Event Timeline

wma_semihalf.com retitled this revision from to Fix possible coherency issues between PEs related to I-cache.
wma_semihalf.com updated this object.
wma_semihalf.com edited the test plan for this revision. (Show Details)
wma_semihalf.com added reviewers: andrew, emaste, zbb.
wma_semihalf.com set the repository for this revision to rS FreeBSD src repository - subversion.
wma_semihalf.com added a subscriber: freebsd-arm-list.
andrew edited edge metadata.
This revision is now accepted and ready to land.Jul 17 2015, 9:32 AM
This revision was automatically updated to reflect the committed changes.