ARM64 TCR register update

[wma_semihalf.com]

Summary

This commit adds proper cache and shareability attributes to
the TCR registers.
Set memory attributes to Normal, outer and inner cacheable WBWA.
Set shareability to inner and outer shareable when SMP is enabled.

[andrew]

Why do you need to pass in the shareability attribute? It's needed for notmal memory, and ignored in device memory so we can add it unconditionally.

[wma_semihalf.com]

Agreed.

[andrew]

sys/arm64/arm64/locore.S

48–52 ↗

(On Diff #6962)

Is this still needed?

191 ↗

(On Diff #6962)

This looks to be unrelated to the rest of the change.

[wma_semihalf.com]

sys/arm64/arm64/locore.S

48–52 ↗

(On Diff #6962)

You're right, I'll remove it prior submitting.

191 ↗

(On Diff #6962)

It's the part of locore fixes described in the patch summary

• secondary stack calculation is modified to provide stack_top = secondary_stacks + (cpu_id)*PAGE_SIZE*KSTACK_PAGES because on ARMv8 the stack grows into lower memory addresses

Please let me know if I should split this patch into two (include+stack and TCR reg) or leave as a one.