This follows the gic and ti/aintc code by adding additional barriers to the
Amlogic pic driver.
Details
Details
- Reviewers
ganbold
Tested on YYHD18 (aml8726-m3 SoC) ... config files coming soon.
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Diff Detail
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- rS FreeBSD src repository - subversion
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I don't believe so and the gic as well as the ti/aintc arm_mask_irq routines
do not currently call arm_irq_memory_barrier.
The intent of arm_irq_memory_barrier is to ensure any device driver writes
have hit the hardware (thus clearing the device's interrupt line) before
the interrupt controller unmasks the interrupt.