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Implement pic_pre_ithread(), pic_post_ithread()
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Authored by br on Apr 4 2019, 12:17 PM.
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Details

Summary

These are required to properly handle interrupts in the interrupt thread.

Instead of disable/enable interrupts in pre_ithread()/post_ithread() respectively, play with priority register (priority 0 effectively disables interrupt on all the cores).

Test Plan

Tested with Cadence network adapter on HiFive Unleashed

Diff Detail

Repository
rS FreeBSD src repository - subversion
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Event Timeline

This revision is now accepted and ready to land.Apr 4 2019, 11:05 PM
This revision was automatically updated to reflect the committed changes.