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Differential D1812

Resolve cache line size from CP15
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Authored by zbb on Feb 9 2015, 11:59 AM.
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Reviewers
andrew
imp
• ian
Summary

Switch the cache line size during invalidations/flushes to be read from CP15 cache type register.

Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf

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zbb updated this revision to Diff 3710.Feb 9 2015, 11:59 AM
zbb retitled this revision from to Resolve cache line size from CP15.
zbb updated this object.
zbb edited the test plan for this revision. (Show Details)
zbb added reviewers: • ian, andrew.
zbb added a subscriber: Unknown Object (MLST).
imp accepted this revision.Feb 9 2015, 3:31 PM
imp added a reviewer: imp.
imp added a subscriber: imp.

This looks good to me... Please commit.

Extra bonus points if you KASSERT at some early time during the init if USB_HOST_ALIGN is smaller than arm_dcache_line_size.

This revision is now accepted and ready to land.Feb 9 2015, 3:31 PM
• ian accepted this revision.Feb 9 2015, 9:30 PM
• ian edited edge metadata.

This is likely to fix a variety of mysterious problems we've been more or less ignoring lately, please commit asap.

zbb closed this revision.Feb 10 2015, 6:16 PM

Thank you!

Committed to r278518
https://svnweb.freebsd.org/changeset/base/278518

Revision Contents
Changeset List

PathSize
sys/
arm/
arm/
12 lines
27 lines
12 lines
include/
3 lines

Diff 3710

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sys/arm/arm/cpufunc.c

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sys/arm/arm/cpufunc_asm_armv7.S

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sys/arm/arm/elf_trampoline.c

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sys/arm/include/armreg.h

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