Switch the cache line size during invalidations/flushes to be read from CP15 cache type register.
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
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| Differential D1812 Authored by zbb on Feb 9 2015, 11:59 AM.
Details
Diff Detail
Event Timelinezbb updated this object. Comment Actions This looks good to me... Please commit. Extra bonus points if you KASSERT at some early time during the init if USB_HOST_ALIGN is smaller than arm_dcache_line_size. This revision is now accepted and ready to land.Feb 9 2015, 3:31 PM2015-02-09 15:31:25 (UTC+0) • ian edited edge metadata. Comment ActionsThis is likely to fix a variety of mysterious problems we've been more or less ignoring lately, please commit asap.
Revision Contents
Diff 3710 sys/arm/arm/cpufunc.c
sys/arm/arm/cpufunc_asm_armv7.S
sys/arm/arm/elf_trampoline.c
sys/arm/include/armreg.h
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