Enhance qpi.c to make it usable on all Core-microarchitecture Xeons.

[kib]

Summary

Existing qpi.c makes too many assumptions about the uncore configuration buses location and about slots occupied. Also it restricts itself only to Nehalem CPUs. It should be useful on all Core-based Xeons. On the 2600 v2 (Ivy) machine I have access to, the buses have numbers 31 (BSP socket) and 63 (second socket), and there is no functions pci0.31.0.0 or pci0.63. According to EDS, all devices on the uncore bus occupy slot >= 8.

Scan all buses, not stopping on the first failed match. Scan all slots for function 0 on the found bus, for instance on Ivy there the slot 0 is not decoded at all. Since the scan is quite unsafe, and access to the buses is mostly useful for developers, enable the csr buses scan with the tunable.

Practically, the attach to config buses is required for the intel-pcm pcm-memory.x tool to work, for instance.

I wonder whether qpi attach should have lower priority to ensure that other bus drivers already attached, so that we do not force some innocent normal PCI bus under qpi.

Test Plan

On two-socket Ivy with devinfo I see two pci buses under qpi0, as expected. Also, pciconf -lvc shows the devices which I want to access, for instance

none101@pci0:31:19:4:	class=0x088000 card=0x18a8103c chip=0x0e818086 rev=0x04 hdr=0x00
    vendor     = 'Intel Corporation'
    device     = 'Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Registers'
    class      = base peripheral
none102@pci0:31:19:5:	class=0x110100 card=0x18a8103c chip=0x0e368086 rev=0x04 hdr=0x00
    vendor     = 'Intel Corporation'
    device     = 'Xeon E7 v2/Xeon E5 v2/Core i7 QPI Ring Performance Ring Monitoring'
    class      = dasp
    subclass   = performance counters
none103@pci0:31:22:0:	class=0x088000 card=0x18a8103c chip=0x0ec88086 rev=0x04 hdr=0x00
    vendor     = 'Intel Corporation'
    device     = 'Xeon E7 v2/Xeon E5 v2/Core i7 System Address Decoder'
    class      = base peripheral

The pcm-memory.x works on the patched kernel while it refuses to start on unpatched one.

[kib]

Update after whitespace fixes committed.

[jhb]

The reason for the original restrictions (Nehalem only, etc.) was out of an abundance of caution. We should have some good way of ensuring we only do this probe later than ACPI. Right now there isn't an easy way to do that until we use multipass more on x86 (at least that I can think of).

sys/x86/pci/qpi.c

116 ↗

(On Diff #32795)

This comment should be updated since we now check every possible slot.

120 ↗

(On Diff #32795)

Maybe use PCIR_SLOTMAX (or whatever the constant is called) rather than the bare 0x20?

[kib]

sys/x86/pci/qpi.c

120 ↗

(On Diff #32795)

PCI_SLOTMAX. Then PCI_BUSMAX should be used instead of 255.

[kib]

Use PCI_SLOTMAX.
Adjust comment.