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pci: fix write order when sizing BARs
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Authored by royger on Jul 27 2017, 10:04 AM.
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Details

Summary

According to the PCI Local Specification rev. 3.0 in case of a 64-bit
BAR both the low and the high parts of the register should be set to
~0 before attempting to read back the size.

So far I have found no single device that has problems with the
previous approach, but I think it's better to stay on the safe size.

This commit should not introduce any functional change.

Sponsored by: Citrix Systems R&D

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rS FreeBSD src repository - subversion
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Event Timeline

This revision is now accepted and ready to land.Jul 27 2017, 3:41 PM
This revision was automatically updated to reflect the committed changes.