MFC r350842, r350844-r350846, r351099, r352848, r352859

r350842:
allwinner: Rework the BUS_PASS on drivers

• Put all clock and control unit driver in BUS_PASS_RESOURCE except for the DE2 CCU as it needs the main CCU to be available.
• Use BUS_PASS_CPU for a20_cpu_cfg as it makes more sense.
• For aw_syscon use SCHEDULER pass as we need it early for drivers that attach in BUS_PASS_SUPPORTDEV
• For the rest we can use BUS_PASS_SUPPORTDEV

r350844:
allwinner: Add a new clock aw_clk_m

We used the aw_clk_nm clock for clock with only one divider factor
and used a fake multiplier factor. This cannot work properly as we
end up writing the "fake" factor to the register (and so always set
the LSB to 1).
Create a new clock for those.
The reason for not using the clk_div clock is because those clocks are
a bit special. Since they are (almost) all related to video we also need
to set the parent clock (the main PLL) to a frequency that they can support.
As the main PLL have some minimal frequency that they can support we need to
be able to set the main PLL to a multiple of the desired frequency.
Let say you want to have a 71Mhz pixel clock (typical for a 1280x800 display)
and the main PLL cannot go under 192Mhz, you need to set it to 3 times the
desired frequency and set the divider to 3 on the hdmi clock.
So this also introduce the CLK_SET_ROUND_MULTIPLE flag that allow for this kind
of scenario.

r350845:
Remove some duplicate code that end up in r350844

r350846:
allwinner: Add support to min/max in aw_clk_frac

The Fractionals clock in Allwinner device have some min/max frequencies
that they can do.
Add support for it.

r351099:
arm: allwinner: Set aw_ccu to BUS_PASS_BUS

In r350842 I've switched the bus pass to resource so it matches the other
clock drivers but this cannot work as this drivers is meant to match
the dts node '/clocks' and if we don't do it at this pass simplebus is
catching this node and we cannot attach.
This solve booting on Allwinner boards that are still using /clocks (A20 SoC)

r352848:
arm64: allwinner: a64: Add PLL_MIPI

PLL_MIPI is the last important PLL that we missed.
Add support for it.
Since it's one of the possible parent for TCON0 also add this clock
now that we can.
While here add some info about what video related clocks should be
enabled at boot and with what frequency.

r352859:
arm: allwinner: Add pll_mipi to the files