Add a new sysctl, hw.altera_jtag_uart.ac_poll_delay, which allows the
(default 10ms) delay associated with a full JTAG UART buffer combined
with a lack of a JTAG-present flag to be tuned.  Setting this higher
may cause some JTAG configurations to be more reliable when printing
out low-level console output at a speed greater than the JTAG UART is
willing to carry data.  Or it may not.

Minor improvements to the Altera JTAG UART device driver:

- Minor rework to the logic to detect JTAG presence in order to be a bit
  more resilient to inevitable races: increase the retry period from two
  seconds to four seconds for trying to find JTAG, and more agressively
  clear the miss counter if JTAG has been reconnected.  Once JTAG has
  vanished, stop prodding the miss counter.

- Do a bit of reworking of the output code to frob the control register
  less by checking whether write interrupts are enabled/disabled before
  changing their state.  This should reduce the opportunity for races
  with JTAG discovery (which are inherent to the Altera
  hardware-software interface, but can at least be minimised).

- Add statistics relating to interrupt enable/disable/JTAG
  discovery/etc.

With these changes, polled-mode JTAG UART ttys appear substantially
more robust.