Sync instruction cache's after writing user breakpoints on MIPS.

Add an implementation for pmaps_sync_icache() on MIPS that sync's the
instruction cache on all CPUs via smp_rendezvous() after a debugger
inserts a breakpoint via ptrace(PT_IO).

Tested by: kan (on Creator CI20 running Ingenic JZ4780 SOC)
MFC after: 2 weeks
Sponsored by: DARPA / AFRL