ARM: create new memory attribute for writethrough cacheable memory.

• add new TEX class for WT cacheable memory
• export new TEX class to kernel as VM_MEMATTR_WT attribute
• add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code

Note:
Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
WT requests is treated as uncacheable.

Approved by: kib (mentor)