Emulate the 'bit test' instruction.
Re-implement RTC current time calculation to eliminate the possibility of
Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs.
When an instruction cannot be decoded just return to userspace so bhyve(8)
can dump the instruction bytes.
Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>.
Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs are
Relax limits when transitioning a vector from the IRR to the ISR and also
when extinguishing it from the ISR in response to an EOI.
Advertise an additional memory BAR in the "dummy" device emulation.
Emulate machine check related MSRs to allow guest OSes like Windows to boot.
Don't advertise the Intel SMX capability to the guest.
Emulate the 'CMP r/m8, imm8' instruction.
Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE.
Emulate guest writes to EFER_MSR properly.
Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup().
Check 'td_owepreempt' and yield the vcpu thread if it is set.
Allow byte reads of AHCI registers.
Handling indirect descriptors is a capability of the host and not one that
needs to be negotiated. Use the host capabilities field and not the negotiated
field when verifying that indirect descriptors are supported.
Allow configuration of the sector size advertised to the guest.
Set the subvendor field in config space to the vendor ID. This is required
by the Windows virtio drivers to correctly match a device.
Bump the size of the blockif scatter-gather list to 67.
Fix off-by-one in array index bounds check. bhyveload would allow you to
create 33 entries on an array that only has 32 slots
Temporarily revert r282922 which bumped the max descriptors.
Emulate the "CMP r/m, reg" instruction (opcode 39H).
Add an option "--get-vmcs-exit-inst-length" to display the instruction length
of the instruction that caused the VM-exit.
Change the header type of the emulated host-bridge from type 1 to type 0.
Don't rely on the 'VM-exit instruction length' field in the VMCS to always
have an accurate length on an EPT violation.
Remove bogus verification of instruction length after instruction decode.
Exceptions don't deliver an error code in real mode.
Fix non-deterministic delays when accessing a vcpu that was in "running" or
Use tunable 'hw.vmm.svm.features' to disable specific SVM features even
though they might be available in hardware. Use tunable 'hw.vmm.svm.num_asids'
to limit the number of ASIDs used by the hypervisor.
Fix regression in 'verify_gla()' with the RIP-relative addressing mode.
Support guest writes to the TSC by enabling the "use TSC offsetting"