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MFC 276724:

Description

MFC 276724:
On some Intel CPUs with a P-state but not C-state invariant TSC the TSC
may also halt in C2 and not just C3 (it seems that in some cases the BIOS
advertises its C3 state as a C2 state in _CST). Just play it safe and
disable both C2 and C3 states if a user forces the use of the TSC as the
timecounter on such CPUs.

PR: 192316

Details

Provenance
jhbAuthored on
Parents
rS280972: Try to unbreak the build after r280971 by providing the missing
Branches
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