Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: ian, imp
Obtained from: Semihalf
Description
Description
Details
Details
- Provenance
zbb Authored on - Reviewer
- • ian
- Parents
- rS278517: MFC r278105:
- Branches
- Unknown
- Tags