New port: devel/yosys
Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.
WWW: http://www.clifford.at/yosys/
PR: 227591
Submitted by: Johnny Sorocil <jsorocil@gmail.com>
Differential Revision: https://reviews.freebsd.org/D15632