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New port: devel/yosys

Description

New port: devel/yosys

Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.

WWW: http://www.clifford.at/yosys/

PR: 227591
Submitted by: Johnny Sorocil <jsorocil@gmail.com>
Differential Revision: https://reviews.freebsd.org/D15632

Details

Committed
tobikJun 6 2018, 2:19 PM
Differential Revision
D15632: Open source toolchain for Lattice ICE40 FPGAs
Parents
rP471843: Fix www/qt5-webengine to build on ARM
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