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Oct 28 2020, 5:46 PM (4 w, 2 d)

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Thu, Oct 29

cyprien_cypou.net added a comment to D26975: Enable IPIs on CPU 0 on arm and arm64.

IHI0048A for the GICv1 Architecture Specification, Chapter 4.3.6 on the Interrupt Clear-Enable Registers (ICDICERn):

Thu, Oct 29, 11:25 PM
cyprien_cypou.net added a comment to D26975: Enable IPIs on CPU 0 on arm and arm64.
In D26975#602470, @mmel wrote:

But, please, can you post full verbose bool log from this system? Thanks.

Thu, Oct 29, 11:16 PM
cyprien_cypou.net added a comment to D26975: Enable IPIs on CPU 0 on arm and arm64.
In D26975#602470, @mmel wrote:

I think from GICv2 it would be assumed that the OS could write to the SGI bits. Software cannot know all existing implementations.

I'm sorry but my interpretation of this fact is exactly opposite. Because software cannot know all existing implementations (thus it cannot predict exact functionality of these bits) we are not allowed to blindly change it. Mainly if TRM for given parts exactly specifies this register as RO...

Thu, Oct 29, 11:05 PM

Oct 28 2020

cyprien_cypou.net added a comment to D26975: Enable IPIs on CPU 0 on arm and arm64.
In D26975#602006, @mmel wrote:

I think that calling gic_irq_mask() for SGIs is redundant and potentially dangerous, we should remove it (or eventually, make it specific only for exact GIC implementation .
The right place for doing same on boot CPU is arm_gic_attach() again only conditionally for specific version.

Oct 28 2020, 6:00 PM