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Differential D53232

riscv: explicit memory barrier primitives
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Authored by mengzhuo1203_gmail.com on Oct 21 2025, 9:45 AM.
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jrtc27

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jrtc27
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riscv
Summary

FreeBSD didn't follow Linux premitives as RISC-V spec required
we use smp_(r|w)mb

|     	| FreeBSD 	| Linux      	|
|-----	|---------	|------------	|
| mb  	| rw, rw  	| iorw, iorw 	|
| rmb 	| r, r    	| ior, ior   	|
| wmb 	| w, w    	| iow, iow   	|

This change explicit this difference.

PR 290249

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mengzhuo1203_gmail.com requested review of this revision.Oct 21 2025, 9:45 AM
mengzhuo1203_gmail.com created this revision.
jrtc27 added a subscriber: jrtc27.Oct 21 2025, 9:53 AM

Do we actually have a proper definition of what *our* memory barrier APIs are meant to mean? What the ISA manual says is a sensible mapping isn't necessarily what we want; note that the table you're referencing is for "Linux memory primitives", and we are not Linux, nor do we follow its memory model.

sys/riscv/include/atomic.h
41

I'm surprised this even works, but I guess if " is just a token to the preprocessor I can kind of see how it might (though would expect the space to go missing). Surely it should be "fence "#PRE", "#SUC?

jrtc27 added a reviewer: jrtc27.Oct 21 2025, 9:53 AM
mengzhuo1203_gmail.com added a comment.Oct 22 2025, 2:12 AM
In D53232#1216063, @jrtc27 wrote:

Do we actually have a proper definition of what *our* memory barrier APIs are meant to mean? What the ISA manual says is a sensible mapping isn't necessarily what we want; note that the table you're referencing is for "Linux memory primitives", and we are not Linux, nor do we follow its memory model.

Thanks for review, it's first time that I contribute to kernel and I trying to fix the https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=290249

I found those definitions are essential to busdma (sys/riscv/riscv/busdma_bounce.c), I will send those diffs later.

As for memory barrier APIs, I can't find them though Google and gpts, can you send the links for me?

Thanks

mengzhuo1203_gmail.com updated this revision to Diff 164723.Oct 22 2025, 4:57 AM
mengzhuo1203_gmail.com retitled this revision from riscv: memory primitives to RISC-V primitives to riscv: explicit memory barrier primitives.
mengzhuo1203_gmail.com edited the summary of this revision. (Show Details)

@jrtc27 I've update the revision, PTAL

jrtc27 added a comment.Oct 22 2025, 9:47 AM

This will not fix that bug. fence is fence iorw, iorw, so all you are doing is relaxing some ordering requirements.

mengzhuo1203_gmail.com updated this revision to Diff 164833.Oct 23 2025, 1:50 AM
mengzhuo1203_gmail.com marked an inline comment as done.
In D53232#1216532, @jrtc27 wrote:

This will not fix that bug. fence is fence iorw, iorw, so all you are doing is relaxing some ordering requirements.

Done.

mengzhuo1203_gmail.com updated this revision to Diff 164847.Oct 23 2025, 4:48 AM

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Diff 164847

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sys/riscv/include/atomic.h

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