Differential D4185

wpi(4): import rS289674
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Authored by avos on Nov 16 2015, 9:25 PM.

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adrian

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rS290950: wpi(4): import r289674

Summary

Switch PCI register reads from using magic numbers to using the names defined in pcireg.h

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rS FreeBSD src repository - subversion

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avos updated this revision to Diff 10245.Nov 16 2015, 9:25 PM

avos retitled this revision from to wpi(4): import rS289674.

avos updated this object.

avos edited the test plan for this revision. (Show Details)

avos added a reviewer: adrian.

avos set the repository for this revision to rS FreeBSD src repository - subversion.

Herald added a subscriber: imp. · View Herald TranscriptNov 16 2015, 9:25 PM

looks good, commit away!

This revision is now accepted and ready to land.Nov 16 2015, 9:40 PM

Closed by commit rS290950: wpi(4): import r289674 (authored by avos). · Explain WhyNov 16 2015, 9:55 PM

This revision was automatically updated to reflect the committed changes.

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sys/

dev/

wpi/

if_wpi.c

8 lines

Diff 10245

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sys/dev/wpi/if_wpi.c

Show First 20 Lines • Show All 3,785 Lines • ▼ Show 20 Lines	if (dtim <= 10)
pmgt = &wpi_pmgt[0][level];		pmgt = &wpi_pmgt[0][level];
else		else
pmgt = &wpi_pmgt[1][level];		pmgt = &wpi_pmgt[1][level];

memset(&cmd, 0, sizeof cmd);		memset(&cmd, 0, sizeof cmd);
if (level != 0) /* not CAM */		if (level != 0) /* not CAM */
cmd.flags \|= htole16(WPI_PS_ALLOW_SLEEP);		cmd.flags \|= htole16(WPI_PS_ALLOW_SLEEP);
/* Retrieve PCIe Active State Power Management (ASPM). */		/* Retrieve PCIe Active State Power Management (ASPM). */
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);		reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);
if (!(reg & 0x1)) /* L0s Entry disabled. */		if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */
cmd.flags \|= htole16(WPI_PS_PCI_PMGT);		cmd.flags \|= htole16(WPI_PS_PCI_PMGT);

cmd.rxtimeout = htole32(pmgt->rxtimeout * IEEE80211_DUR_TU);		cmd.rxtimeout = htole32(pmgt->rxtimeout * IEEE80211_DUR_TU);
cmd.txtimeout = htole32(pmgt->txtimeout * IEEE80211_DUR_TU);		cmd.txtimeout = htole32(pmgt->txtimeout * IEEE80211_DUR_TU);

if (dtim == 0) {		if (dtim == 0) {
dtim = 1;		dtim = 1;
skip_dtim = 0;		skip_dtim = 0;
▲ Show 20 Lines • Show All 1,317 Lines • ▼ Show 20 Lines	wpi_apm_init(struct wpi_softc *sc)
WPI_SETBITS(sc, WPI_GIO_CHICKEN, WPI_GIO_CHICKEN_DIS_L0S_TIMER);		WPI_SETBITS(sc, WPI_GIO_CHICKEN, WPI_GIO_CHICKEN_DIS_L0S_TIMER);
/* Don't wait for ICH L0s (ICH bug workaround). */		/* Don't wait for ICH L0s (ICH bug workaround). */
WPI_SETBITS(sc, WPI_GIO_CHICKEN, WPI_GIO_CHICKEN_L1A_NO_L0S_RX);		WPI_SETBITS(sc, WPI_GIO_CHICKEN, WPI_GIO_CHICKEN_L1A_NO_L0S_RX);

/* Set FH wait threshold to max (HW bug under stress workaround). */		/* Set FH wait threshold to max (HW bug under stress workaround). */
WPI_SETBITS(sc, WPI_DBG_HPET_MEM, 0xffff0000);		WPI_SETBITS(sc, WPI_DBG_HPET_MEM, 0xffff0000);

/* Retrieve PCIe Active State Power Management (ASPM). */		/* Retrieve PCIe Active State Power Management (ASPM). */
reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);		reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 1);
/* Workaround for HW instability in PCIe L0->L0s->L1 transition. */		/* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
if (reg & 0x02) /* L1 Entry enabled. */		if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */
WPI_SETBITS(sc, WPI_GIO, WPI_GIO_L0S_ENA);		WPI_SETBITS(sc, WPI_GIO, WPI_GIO_L0S_ENA);
else		else
WPI_CLRBITS(sc, WPI_GIO, WPI_GIO_L0S_ENA);		WPI_CLRBITS(sc, WPI_GIO, WPI_GIO_L0S_ENA);

WPI_SETBITS(sc, WPI_ANA_PLL, WPI_ANA_PLL_INIT);		WPI_SETBITS(sc, WPI_ANA_PLL, WPI_ANA_PLL_INIT);

/* Wait for clock stabilization before accessing prph. */		/* Wait for clock stabilization before accessing prph. */
if ((error = wpi_clock_wait(sc)) != 0)		if ((error = wpi_clock_wait(sc)) != 0)
▲ Show 20 Lines • Show All 505 Lines • Show Last 20 Lines

wpi(4): import rS289674ClosedPublicActions