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lib/msun/powerpc/fenv.h
Show All 36 Lines | |||||
#ifndef __fenv_static | #ifndef __fenv_static | ||||
#define __fenv_static static | #define __fenv_static static | ||||
#endif | #endif | ||||
typedef __uint32_t fenv_t; | typedef __uint32_t fenv_t; | ||||
typedef __uint32_t fexcept_t; | typedef __uint32_t fexcept_t; | ||||
/* Exception flags */ | /* Exception flags */ | ||||
#ifdef __SPE__ | |||||
#define FE_OVERFLOW 0x00000100 | |||||
#define FE_UNDERFLOW 0x00000200 | |||||
#define FE_DIVBYZERO 0x00000400 | |||||
#define FE_INVALID 0x00000800 | |||||
#define FE_INEXACT 0x00001000 | |||||
#define FE_ALL_INVALID FE_INVALID | |||||
alfredo: Should it include FE_INVALID? Like:
```
#define FE_ALL_INVALID FE_INVALID
```
| |||||
Done Inline ActionsYes, it should be. jhibbits: Yes, it should be. | |||||
#define _FPUSW_SHIFT 6 | |||||
#else | |||||
#define FE_INEXACT 0x02000000 | #define FE_INEXACT 0x02000000 | ||||
#define FE_DIVBYZERO 0x04000000 | #define FE_DIVBYZERO 0x04000000 | ||||
#define FE_UNDERFLOW 0x08000000 | #define FE_UNDERFLOW 0x08000000 | ||||
#define FE_OVERFLOW 0x10000000 | #define FE_OVERFLOW 0x10000000 | ||||
#define FE_INVALID 0x20000000 /* all types of invalid FP ops */ | #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ | ||||
/* | /* | ||||
* The PowerPC architecture has extra invalid flags that indicate the | * The PowerPC architecture has extra invalid flags that indicate the | ||||
Show All 9 Lines | |||||
#define FE_VXIMZ 0x00100000 /* inf * 0 */ | #define FE_VXIMZ 0x00100000 /* inf * 0 */ | ||||
#define FE_VXZDZ 0x00200000 /* 0 / 0 */ | #define FE_VXZDZ 0x00200000 /* 0 / 0 */ | ||||
#define FE_VXIDI 0x00400000 /* inf / inf */ | #define FE_VXIDI 0x00400000 /* inf / inf */ | ||||
#define FE_VXISI 0x00800000 /* inf - inf */ | #define FE_VXISI 0x00800000 /* inf - inf */ | ||||
#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ | #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ | ||||
#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ | #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ | ||||
FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ | FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ | ||||
FE_VXSNAN | FE_INVALID) | FE_VXSNAN | FE_INVALID) | ||||
#define _FPUSW_SHIFT 22 | |||||
#endif | |||||
#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ | #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ | ||||
FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) | FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) | ||||
/* Rounding modes */ | /* Rounding modes */ | ||||
#define FE_TONEAREST 0x0000 | #define FE_TONEAREST 0x0000 | ||||
#define FE_TOWARDZERO 0x0001 | #define FE_TOWARDZERO 0x0001 | ||||
#define FE_UPWARD 0x0002 | #define FE_UPWARD 0x0002 | ||||
#define FE_DOWNWARD 0x0003 | #define FE_DOWNWARD 0x0003 | ||||
#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ | #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ | ||||
FE_UPWARD | FE_TOWARDZERO) | FE_UPWARD | FE_TOWARDZERO) | ||||
__BEGIN_DECLS | __BEGIN_DECLS | ||||
/* Default floating-point environment */ | /* Default floating-point environment */ | ||||
extern const fenv_t __fe_dfl_env; | extern const fenv_t __fe_dfl_env; | ||||
#define FE_DFL_ENV (&__fe_dfl_env) | #define FE_DFL_ENV (&__fe_dfl_env) | ||||
/* We need to be able to map status flag positions to mask flag positions */ | /* We need to be able to map status flag positions to mask flag positions */ | ||||
#define _FPUSW_SHIFT 22 | |||||
#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ | #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ | ||||
FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) | FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) | ||||
#ifndef _SOFT_FLOAT | #ifndef _SOFT_FLOAT | ||||
#ifdef __SPE__ | #ifdef __SPE__ | ||||
#define __mffs(__env) \ | #define __mffs(__env) \ | ||||
__asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg)) | __asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg)) | ||||
#define __mtfsf(__env) \ | #define __mtfsf(__env) \ | ||||
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines | if (__excepts & FE_INVALID) | ||||
__excepts |= FE_ALL_INVALID; | __excepts |= FE_ALL_INVALID; | ||||
__mffs(&__r); | __mffs(&__r); | ||||
__r.__bits.__reg &= ~__excepts; | __r.__bits.__reg &= ~__excepts; | ||||
__r.__bits.__reg |= *__flagp & __excepts; | __r.__bits.__reg |= *__flagp & __excepts; | ||||
__mtfsf(__r); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
#ifdef __SPE__ | |||||
extern int feraiseexcept(int __excepts); | |||||
#else | |||||
__fenv_static inline int | __fenv_static inline int | ||||
feraiseexcept(int __excepts) | feraiseexcept(int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
if (__excepts & FE_INVALID) | if (__excepts & FE_INVALID) | ||||
__excepts |= FE_VXSOFT; | __excepts |= FE_VXSOFT; | ||||
__mffs(&__r); | __mffs(&__r); | ||||
__r.__bits.__reg |= __excepts; | __r.__bits.__reg |= __excepts; | ||||
__mtfsf(__r); | __mtfsf(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
#endif | |||||
__fenv_static inline int | __fenv_static inline int | ||||
fetestexcept(int __excepts) | fetestexcept(int __excepts) | ||||
{ | { | ||||
union __fpscr __r; | union __fpscr __r; | ||||
__mffs(&__r); | __mffs(&__r); | ||||
return (__r.__bits.__reg & __excepts); | return (__r.__bits.__reg & __excepts); | ||||
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines |
Should it include FE_INVALID? Like: