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diff --git a/sys/dev/nvme/nvme_ctrlr.c b/sys/dev/nvme/nvme_ctrlr.c
--- a/sys/dev/nvme/nvme_ctrlr.c
+++ b/sys/dev/nvme/nvme_ctrlr.c
@@ -201,8 +201,6 @@
if (ctrlr->quirks & QUIRK_APPLE_SHARED_CID_SPACE)
num_trackers = min(num_trackers,
NVME_ADMIN_ENTRIES - ctrlr->adminq.num_trackers);
- if (ctrlr->quirks & QUIRK_APPLE_S3X_SERIALIZE)
- num_trackers = 1;
/*
* Our best estimate for the maximum number of I/Os that we should
@@ -538,8 +536,6 @@
ctrlr->max_xfer_size = min(ctrlr->max_xfer_size,
1 << (ctrlr->cdata.mdts + NVME_MPS_SHIFT +
NVME_CAP_HI_MPSMIN(ctrlr->cap_hi)));
- if (ctrlr->quirks & QUIRK_APPLE_S3X_SERIALIZE)
- ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 8192U);
return (0);
}
diff --git a/sys/dev/nvme/nvme_pci.c b/sys/dev/nvme/nvme_pci.c
--- a/sys/dev/nvme/nvme_pci.c
+++ b/sys/dev/nvme/nvme_pci.c
@@ -99,8 +99,7 @@
{ 0x07f015ad, 0, 0, "VMware NVMe Controller" },
{ 0x2003106b, 0, 0, "Apple S3X NVMe Controller",
QUIRK_APPLE_NO_ASYNC_EVENT | QUIRK_APPLE_S3X_NS1_ONLY |
- QUIRK_PCIE_FLR_ON_FATAL | QUIRK_APPLE_S3X_SERIALIZE |
- QUIRK_IGNORE_RAB },
+ QUIRK_PCIE_FLR_ON_FATAL | QUIRK_IGNORE_RAB },
{ 0x2005106b, 0, 0, "Apple ANS2 NVMe Controller (T2)",
QUIRK_APPLE_IDENTIFY_CNS_BROKEN | QUIRK_APPLE_SHARED_CID_SPACE |
QUIRK_APPLE_NO_ASYNC_EVENT | QUIRK_APPLE_SINGLE_VECTOR |
diff --git a/sys/dev/nvme/nvme_private.h b/sys/dev/nvme/nvme_private.h
--- a/sys/dev/nvme/nvme_private.h
+++ b/sys/dev/nvme/nvme_private.h
@@ -248,7 +248,6 @@
#define QUIRK_APPLE_S3X_NS1_ONLY 0x200 /* Ignore Apple-internal namespace 2 */
#define QUIRK_APPLE_128_BYTE_SQES 0x400 /* T2 uses 128-byte I/O SQEs */
#define QUIRK_PCIE_FLR_ON_FATAL 0x800 /* Use FLR for a fatal controller */
-#define QUIRK_APPLE_S3X_SERIALIZE 0x1000 /* One S3X I/O at a time */
#define QUIRK_IGNORE_RAB 0x2000 /* Don't configure AB from RAB */
/* Values programmed into CC.IOSQES (log2 of the SQE size in bytes). */

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