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D55097.1794242503.diff
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diff --git a/sys/arm/allwinner/aw_mmc.h b/sys/arm/allwinner/aw_mmc.h
--- a/sys/arm/allwinner/aw_mmc.h
+++ b/sys/arm/allwinner/aw_mmc.h
@@ -58,6 +58,7 @@
#define AW_MMC_IDST 0x88 /* IDMAC Status Register */
#define AW_MMC_IDIE 0x8C /* IDMAC Interrupt Enable Register */
+#define AW_MMC_THLDC 0x100 /* Card threshold control register */
#define AW_MMC_DDR_SBIT_DET 0x10C /* eMMC4.5 DDR Start Bit Detection control register */
#define AW_MMC_DRV_DL 0x140 /* Drive Delay control register */
#define AW_MMC_SAMP_DL 0x144 /* Sample Delay controle register */
@@ -169,6 +170,10 @@
/* AW_MMC_NTSR */
#define AW_MMC_NTSR_MODE_SELECT (1U << 31)
+/* AW_MMC_HWRST */
+#define AW_MMC_HWRST_ASSERT (0U << 0)
+#define AW_MMC_HWRST_DEASSERT (1U << 0)
+
/* IDMA CONTROLLER BUS MOD BIT FIELD */
#define AW_MMC_DMAC_IDMAC_SOFT_RST (1U << 0)
#define AW_MMC_DMAC_IDMAC_FIX_BURST (1U << 1)
@@ -200,6 +205,11 @@
#define AW_MMC_IDST_COMPLETE \
(AW_MMC_IDST_TX_INT | AW_MMC_IDST_RX_INT)
+/* AW_MMC_THLDC */
+#define AW_MMC_THLDC_RD_EN (1U << 1)
+#define AW_MMC_THLDC_WR_EN (1U << 2)
+#define AW_MMC_THLDC_THRESH(x) ((x & 0xFFF) << 16) /* Card read fifo threshold */
+
/* AW_MMC_DDR_SBIT_DET */
#define AW_MMC_DDR_SBIT_HS_MD_EN (1U << 31)
diff --git a/sys/arm/allwinner/aw_mmc.c b/sys/arm/allwinner/aw_mmc.c
--- a/sys/arm/allwinner/aw_mmc.c
+++ b/sys/arm/allwinner/aw_mmc.c
@@ -89,6 +89,7 @@
bool can_calibrate;
bool new_timing;
bool zero_is_skip;
+ uint16_t fifo_threshold;
};
static const struct aw_mmc_conf a10_mmc_conf = {
@@ -117,9 +118,11 @@
static const struct aw_mmc_conf h616_mmc_conf = {
.dma_xferlen = 0x10000,
+ .dma_desc_shift = 2,
.mask_data0 = true,
.can_calibrate = true,
.new_timing = true,
+ .fifo_threshold = 512,
};
static const struct aw_mmc_conf h616_emmc_conf = {
@@ -737,6 +740,19 @@
if (timeout == 0)
return (ETIMEDOUT);
+ if (sc->aw_mmc_conf->fifo_threshold) {
+ /* Reset card */
+ AW_MMC_WRITE_4(sc, AW_MMC_HWRST, AW_MMC_HWRST_ASSERT);
+ DELAY(10);
+ AW_MMC_WRITE_4(sc, AW_MMC_HWRST, AW_MMC_HWRST_DEASSERT);
+ DELAY(300);
+
+ /* Setup FIFO R/W threshold */
+ AW_MMC_WRITE_4(sc, AW_MMC_THLDC,
+ AW_MMC_THLDC_THRESH(sc->aw_mmc_conf->fifo_threshold) |
+ AW_MMC_THLDC_WR_EN | AW_MMC_THLDC_RD_EN);
+ }
+
return (0);
}

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