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D61018.1793773944.diff
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D61018.1793773944.diff
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diff --git a/sys/dev/dwc/dwc4_dma.c b/sys/dev/dwc/dwc4_dma.c
--- a/sys/dev/dwc/dwc4_dma.c
+++ b/sys/dev/dwc/dwc4_dma.c
@@ -623,10 +623,28 @@
dma4_init(struct dwc_softc *sc)
{
struct mbuf *m;
+ bus_addr_t lowaddr;
uint32_t reg;
+ u_int addr_bits;
int error;
int idx;
+ /* The address width of the DMA is a synthesis option of the core. */
+ reg = READ4(sc, ETH_MACHWF1R);
+ switch ((reg & MACHWF1R_ADDR64_M) >> MACHWF1R_ADDR64_S) {
+ case 1:
+ addr_bits = 40;
+ break;
+ case 2:
+ addr_bits = 48;
+ break;
+ default:
+ addr_bits = 32;
+ break;
+ }
+ lowaddr = (bus_addr_t)MIN(((uint64_t)1 << addr_bits) - 1,
+ (uint64_t)BUS_SPACE_MAXADDR);
+
WRITE4(sc, ETH_MACQ0TXFCR, 0xffff << 16 | 1);
WRITE4(sc, ETH_MACRXFCR, 1);
@@ -694,7 +712,7 @@
error = bus_dma_tag_create(
bus_get_dma_tag(sc->dev), /* Parent tag. */
DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
- BUS_SPACE_MAXADDR, /* lowaddr */
+ lowaddr, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
TX_DESC_SIZE, 1, /* maxsize, nsegments */
@@ -729,7 +747,7 @@
error = bus_dma_tag_create(
bus_get_dma_tag(sc->dev), /* Parent tag. */
1, 0, /* alignment, boundary */
- BUS_SPACE_MAXADDR, /* lowaddr */
+ lowaddr, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MCLBYTES * TX_MAP_MAX_SEGS, /* maxsize */
@@ -768,7 +786,7 @@
error = bus_dma_tag_create(
bus_get_dma_tag(sc->dev), /* Parent tag. */
DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
- BUS_SPACE_MAXADDR, /* lowaddr */
+ lowaddr, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
RX_DESC_SIZE, 1, /* maxsize, nsegments */
@@ -803,7 +821,7 @@
error = bus_dma_tag_create(
bus_get_dma_tag(sc->dev), /* Parent tag. */
1, 0, /* alignment, boundary */
- BUS_SPACE_MAXADDR, /* lowaddr */
+ lowaddr, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MCLBYTES, 1, /* maxsize, nsegments */
diff --git a/sys/dev/dwc/dwc4_reg.h b/sys/dev/dwc/dwc4_reg.h
--- a/sys/dev/dwc/dwc4_reg.h
+++ b/sys/dev/dwc/dwc4_reg.h
@@ -76,6 +76,8 @@
#define ETH_MACDR 0x0114
#define ETH_MACHWF0R 0x011C
#define ETH_MACHWF1R 0x0120
+#define MACHWF1R_ADDR64_S 14 /* Address Width */
+#define MACHWF1R_ADDR64_M (0x3 << MACHWF1R_ADDR64_S)
#define ETH_MACHWF2R 0x0124
#define ETH_MACHWF3R 0x0128
#define ETH_MACMDIOAR 0x0200
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D61018.1793773944.diff (2 KB)
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D61018: dwc: Limit the DMA of the QoS core to the address width of the hardware
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