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diff --git a/sys/arm64/arm64/gic_v3.c b/sys/arm64/arm64/gic_v3.c
--- a/sys/arm64/arm64/gic_v3.c
+++ b/sys/arm64/arm64/gic_v3.c
@@ -1255,7 +1255,7 @@
{
/* Set prority mask */
- gic_icc_write(PMR, mask & ICC_PMR_EL1_PRIO_MASK);
+ gic_icc_write(PMR, mask & ICC_PMR_Priority_MASK);
}
static int
@@ -1270,14 +1270,14 @@
* via system registers.
*/
sre = READ_SPECIALREG(icc_sre_el1);
- sre |= ICC_SRE_EL1_SRE;
+ sre |= ICC_SRE_SRE;
WRITE_SPECIALREG(icc_sre_el1, sre);
isb();
/*
* Now ensure that the bit is set.
*/
sre = READ_SPECIALREG(icc_sre_el1);
- if ((sre & ICC_SRE_EL1_SRE) == 0) {
+ if ((sre & ICC_SRE_SRE) == 0) {
/* We are done. This was disabled in EL2 */
device_printf(sc->dev, "ERROR: CPU%u cannot enable CPU interface "
"via system registers\n", cpuid);
@@ -1303,9 +1303,9 @@
/* Priority mask to minimum - accept all interrupts */
gic_v3_cpu_priority(GIC_PRIORITY_MIN);
/* Disable EOI mode */
- gic_icc_clear(CTLR, ICC_CTLR_EL1_EOIMODE);
+ gic_icc_clear(CTLR, ICC_CTLR_EOImode);
/* Enable group 1 (insecure) interrups */
- gic_icc_set(IGRPEN1, ICC_IGRPEN0_EL1_EN);
+ gic_icc_set(IGRPEN1, ICC_IGRPEN0_Enable);
return (0);
}
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -816,16 +816,16 @@
#define GMID_BS_SIZE(reg) (((reg) & GMID_BS_MASK) >> GMID_BS_SHIFT)
/* ICC_CTLR_EL1 */
-#define ICC_CTLR_EL1_EOIMODE (1U << 1)
+#define ICC_CTLR_EOImode (1U << 1)
/* ICC_IAR1_EL1 */
-#define ICC_IAR1_EL1_SPUR (0x03ff)
+#define ICC_IAR1_SPUR (0x03ff)
/* ICC_IGRPEN0_EL1 */
-#define ICC_IGRPEN0_EL1_EN (1U << 0)
+#define ICC_IGRPEN0_Enable (1U << 0)
/* ICC_PMR_EL1 */
-#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
+#define ICC_PMR_Priority_MASK (0xFFUL)
/* ICC_SGI1R_EL1 */
#define ICC_SGI1R_EL1_op0 3
@@ -857,7 +857,7 @@
#define ICC_SGI1R_Aff3_VAL(x) ((x) & ICC_SGI1R_Aff3_MASK)
/* ICC_SRE_EL1 */
-#define ICC_SRE_EL1_SRE (1U << 0)
+#define ICC_SRE_SRE (1U << 0)
/* ID_AA64AFR0_EL1 */
#define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1)

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