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diff --git a/sys/arm64/iommu/smmu.c b/sys/arm64/iommu/smmu.c
--- a/sys/arm64/iommu/smmu.c
+++ b/sys/arm64/iommu/smmu.c
@@ -623,20 +623,23 @@
struct smmu_cmdq_entry cmd;
struct smmu_queue *q;
int prod;
+ bool msipoll;
q = &sc->cmdq;
prod = q->lc.prod;
+ msipoll = ((sc->options & SMMU_OPT_MSIPOLL) != 0);
+
/* Enqueue sync command. */
memset(&cmd, 0, sizeof(cmd));
cmd.opcode = CMD_SYNC;
- if ((sc->features & SMMU_FEATURE_MSI) != 0) {
+ if (msipoll) {
cmd.sync.msiaddr = q->paddr +
Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8;
}
smmu_cmdq_enqueue_cmd(sc, &cmd);
- if ((sc->features & SMMU_FEATURE_MSI) != 0)
+ if (msipoll)
smmu_sync_wait_msi(sc, q);
else
smmu_sync_wait_poll(sc, q);
@@ -1356,8 +1359,6 @@
uint32_t reg;
uint32_t val;
- sc->features = 0;
-
reg = bus_read_4(sc->res[0], SMMU_IDR0);
if (reg & IDR0_ST_LVL_2) {
@@ -1404,6 +1405,9 @@
if (bootverbose)
device_printf(sc->dev, "MSI feature present.\n");
sc->features |= SMMU_FEATURE_MSI;
+ /* Support polling if we support MSI & are cache-coherent */
+ if ((sc->features & SMMU_FEATURE_COHERENCY) != 0)
+ sc->options |= SMMU_OPT_MSIPOLL;
}
if (reg & IDR0_HYP) {
diff --git a/sys/arm64/iommu/smmu_fdt.c b/sys/arm64/iommu/smmu_fdt.c
--- a/sys/arm64/iommu/smmu_fdt.c
+++ b/sys/arm64/iommu/smmu_fdt.c
@@ -87,6 +87,8 @@
sc->dev = dev;
node = ofw_bus_get_node(dev);
+ if (OF_hasprop(node, "dma-coherent"))
+ sc->features |= SMMU_FEATURE_COHERENCY;
rid = 0;
sc->res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
diff --git a/sys/arm64/iommu/smmuvar.h b/sys/arm64/iommu/smmuvar.h
--- a/sys/arm64/iommu/smmuvar.h
+++ b/sys/arm64/iommu/smmuvar.h
@@ -160,6 +160,10 @@
#define SMMU_FEATURE_VAX (1 << 13)
#define SMMU_FEATURE_COHERENCY (1 << 14)
#define SMMU_FEATURE_RANGE_INV (1 << 15)
+
+ uint32_t options;
+#define SMMU_OPT_MSIPOLL (1 << 0)
+
struct smmu_queue cmdq;
struct smmu_queue evtq;
struct smmu_queue priq;

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