+Ongoing work is happening in the area of schedulers along multiple axes.
+
+We are working on solutions to long-standing ULE shortcomings such as unfainess for non-interactive threads in certain particular circumstances and the very weak effect of nice values.
+It seems difficult to solve the first in full with current ULE's design, so in parallel we have been sketching a new design with the following additional aims:
+
+1. More stable and predictable behavior.
+2. Separately controllable latency and allocated CPU.
+3. Enabling new features like scheduling on hybrid CPUs, power-aware scheduling, hierarchical scheduling, etc. while retaining fairness.
+
+We have also been reviewing the 4BSD and ULE schedulers in detail, leading to some bug fixes, such as:
+
+- Priority conflation of differently-niced CPU-bound threads (4BSD)
+- Priority diminishing too slowly when consuming CPU, because of some obsolete SMP scaling (4BSD)
+- Fix off by one in `preempt_thresh` parameter definition (ULE)
+- Fix selecting lowest priority thread early in some corner cases (ULE)
+- Stop consuming memory linearly with `MAXCPU` for local runqueues (4BSD; by Minsoo Choo).
+
+A presentation was done at BSDCan 2026's Developer Summit on these matters (see link at the top).
+
+On the hybrid scheduling front, a number of reviews have been created by Koine Yuusuke with code to support Intel Hardware Feedback Interface (HFI) and Thread Director (ITD), and a common infrastructure for capacities and scores was proposed by Minsoo Choo.