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D34060.id101990.diff
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Index: sys/arm64/arm64/debug_monitor.c
===================================================================
--- sys/arm64/arm64/debug_monitor.c
+++ sys/arm64/arm64/debug_monitor.c
@@ -189,9 +189,9 @@
KASSERT((READ_SPECIALREG(daif) & PSR_D) == PSR_D,
("%s: debug exceptions are not masked", __func__));
- kdb_frame->tf_spsr |= DBG_SPSR_SS;
+ kdb_frame->tf_spsr |= PSR_SS;
WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) |
- DBG_MDSCR_SS | DBG_MDSCR_KDE);
+ MDSCR_SS | MDSCR_KDE);
/*
* Disable breakpoints and watchpoints, e.g. stepping
@@ -200,7 +200,7 @@
*/
if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) {
WRITE_SPECIALREG(mdscr_el1,
- READ_SPECIALREG(mdscr_el1) & ~DBG_MDSCR_MDE);
+ READ_SPECIALREG(mdscr_el1) & ~MDSCR_MDE);
}
}
@@ -212,16 +212,16 @@
("%s: debug exceptions are not masked", __func__));
WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) &
- ~(DBG_MDSCR_SS | DBG_MDSCR_KDE));
+ ~(MDSCR_SS | MDSCR_KDE));
/* Restore breakpoints and watchpoints */
if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) {
WRITE_SPECIALREG(mdscr_el1,
- READ_SPECIALREG(mdscr_el1) | DBG_MDSCR_MDE);
+ READ_SPECIALREG(mdscr_el1) | MDSCR_MDE);
if ((kernel_monitor.dbg_flags & DBGMON_KERNEL) != 0) {
WRITE_SPECIALREG(mdscr_el1,
- READ_SPECIALREG(mdscr_el1) | DBG_MDSCR_KDE);
+ READ_SPECIALREG(mdscr_el1) | MDSCR_KDE);
}
}
}
@@ -482,7 +482,7 @@
mdscr = READ_SPECIALREG(mdscr_el1);
if ((monitor->dbg_flags & DBGMON_ENABLED) == 0) {
- mdscr &= ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE);
+ mdscr &= ~(MDSCR_MDE | MDSCR_KDE);
} else {
for (i = 0; i < dbg_breakpoint_num; i++) {
dbg_wb_write_reg(DBG_REG_BASE_BCR, i,
@@ -497,9 +497,9 @@
dbg_wb_write_reg(DBG_REG_BASE_WVR, i,
monitor->dbg_wvr[i]);
}
- mdscr |= DBG_MDSCR_MDE;
+ mdscr |= MDSCR_MDE;
if ((monitor->dbg_flags & DBGMON_KERNEL) == DBGMON_KERNEL)
- mdscr |= DBG_MDSCR_KDE;
+ mdscr |= MDSCR_KDE;
}
WRITE_SPECIALREG(mdscr_el1, mdscr);
isb();
@@ -563,8 +563,7 @@
dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
}
WRITE_SPECIALREG(mdscr_el1,
- READ_SPECIALREG(mdscr_el1) &
- ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE));
+ READ_SPECIALREG(mdscr_el1) & ~(MDSCR_MDE | MDSCR_KDE));
isb();
}
}
@@ -597,8 +596,7 @@
dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
}
WRITE_SPECIALREG(mdscr_el1,
- READ_SPECIALREG(mdscr_el1) &
- ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE));
+ READ_SPECIALREG(mdscr_el1) & ~(MDSCR_MDE | MDSCR_KDE));
isb();
}
}
Index: sys/arm64/arm64/exec_machdep.c
===================================================================
--- sys/arm64/arm64/exec_machdep.c
+++ sys/arm64/arm64/exec_machdep.c
@@ -241,10 +241,10 @@
* constrained undefined behaviour. If the user mis-programs
* these, there is no risk to the system.
*/
- ctrl &= DBG_BCR_EN | DBG_BCR_PMC | DBG_BCR_BAS;
- if ((ctrl & DBG_BCR_EN) != 0) {
+ ctrl &= DBGBCR_EN | DBGBCR_PMC | DBGBCR_BAS;
+ if ((ctrl & DBGBCR_EN) != 0) {
/* Only target EL0. */
- if ((ctrl & DBG_BCR_PMC) != DBG_BCR_PMC_EL0)
+ if ((ctrl & DBGBCR_PMC) != DBGBCR_PMC_EL0)
return (EINVAL);
monitor->dbg_enable_count++;
@@ -269,24 +269,24 @@
* Some control fields are ignored, and other bits reserved.
* Only unlinked watchpoints are supported.
*/
- ctrl &= DBG_WCR_EN | DBG_WCR_PAC | DBG_WCR_LSC | DBG_WCR_BAS |
- DBG_WCR_MASK;
+ ctrl &= DBGWCR_EN | DBGWCR_PAC | DBGWCR_LSC | DBGWCR_BAS |
+ DBGWCR_MASK;
- if ((ctrl & DBG_WCR_EN) != 0) {
+ if ((ctrl & DBGWCR_EN) != 0) {
/* Only target EL0. */
- if ((ctrl & DBG_WCR_PAC) != DBG_WCR_PAC_EL0)
+ if ((ctrl & DBGWCR_PAC) != DBGWCR_PAC_EL0)
return (EINVAL);
/* Must set at least one of the load/store bits. */
- if ((ctrl & DBG_WCR_LSC) == 0)
+ if ((ctrl & DBGWCR_LSC) == 0)
return (EINVAL);
/*
* When specifying the address range with BAS, the MASK
* field must be zero.
*/
- if ((ctrl & DBG_WCR_BAS) != DBG_WCR_BAS_MASK &&
- (ctrl & DBG_WCR_MASK) != 0)
+ if ((ctrl & DBGWCR_BAS) != DBGWCR_BAS &&
+ (ctrl & DBGWCR_MASK) != 0)
return (EINVAL);
monitor->dbg_enable_count++;
Index: sys/arm64/arm64/swtch.S
===================================================================
--- sys/arm64/arm64/swtch.S
+++ sys/arm64/arm64/swtch.S
@@ -41,7 +41,7 @@
.macro clear_step_flag pcbflags, tmp
tbz \pcbflags, #PCB_SINGLE_STEP_SHIFT, 999f
mrs \tmp, mdscr_el1
- bic \tmp, \tmp, #1
+ bic \tmp, \tmp, #MDSCR_SS
msr mdscr_el1, \tmp
isb
999:
@@ -50,7 +50,7 @@
.macro set_step_flag pcbflags, tmp
tbz \pcbflags, #PCB_SINGLE_STEP_SHIFT, 999f
mrs \tmp, mdscr_el1
- orr \tmp, \tmp, #1
+ orr \tmp, \tmp, #MDSCR_SS
msr mdscr_el1, \tmp
isb
999:
Index: sys/arm64/arm64/trap.c
===================================================================
--- sys/arm64/arm64/trap.c
+++ sys/arm64/arm64/trap.c
@@ -623,7 +623,7 @@
td->td_frame->tf_spsr &= ~PSR_SS;
td->td_pcb->pcb_flags &= ~PCB_SINGLE_STEP;
WRITE_SPECIALREG(mdscr_el1,
- READ_SPECIALREG(mdscr_el1) & ~DBG_MDSCR_SS);
+ READ_SPECIALREG(mdscr_el1) & ~MDSCR_SS);
call_trapsignal(td, SIGTRAP, TRAP_TRACE,
(void *)frame->tf_elr, exception);
userret(td, frame);
Index: sys/arm64/include/armreg.h
===================================================================
--- sys/arm64/include/armreg.h
+++ sys/arm64/include/armreg.h
@@ -133,6 +133,44 @@
#define DAIF_INTR (DAIF_I) /* All exceptions that pass */
/* through the intr framework */
+/* DBGBCR<n>_EL1 - Debug Watchpoint Control Registers */
+#define DBGBCR_EN 0x1
+#define DBGBCR_PMC_SHIFT 1
+#define DBGBCR_PMC (0x3 << DBGBCR_PMC_SHIFT)
+#define DBGBCR_PMC_EL1 (0x1 << DBGBCR_PMC_SHIFT)
+#define DBGBCR_PMC_EL0 (0x2 << DBGBCR_PMC_SHIFT)
+#define DBGBCR_BAS_SHIFT 5
+#define DBGBCR_BAS (0xf << DBGBCR_BAS_SHIFT)
+#define DBGBCR_HMC_SHIFT 13
+#define DBGBCR_HMC (0x1 << DBGBCR_HMC_SHIFT)
+#define DBGBCR_SSC_SHIFT 14
+#define DBGBCR_SSC (0x3 << DBGBCR_SSC_SHIFT)
+#define DBGBCR_LBN_SHIFT 16
+#define DBGBCR_LBN (0xf << DBGBCR_LBN_SHIFT)
+#define DBGBCR_BT_SHIFT 20
+#define DBGBCR_BT (0xf << DBGBCR_BT_SHIFT)
+
+/* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */
+#define DBGWCR_EN 0x1
+#define DBGWCR_PAC_SHIFT 1
+#define DBGWCR_PAC (0x3 << DBGWCR_PAC_SHIFT)
+#define DBGWCR_PAC_EL1 (0x1 << DBGWCR_PAC_SHIFT)
+#define DBGWCR_PAC_EL0 (0x2 << DBGWCR_PAC_SHIFT)
+#define DBGWCR_LSC_SHIFT 3
+#define DBGWCR_LSC (0x3 << DBGWCR_LSC_SHIFT)
+#define DBGWCR_BAS_SHIFT 5
+#define DBGWCR_BAS (0xff << DBGWCR_BAS_SHIFT)
+#define DBGWCR_HMC_SHIFT 13
+#define DBGWCR_HMC (0x1 << DBGWCR_HMC_SHIFT)
+#define DBGWCR_SSC_SHIFT 14
+#define DBGWCR_SSC (0x3 << DBGWCR_SSC_SHIFT)
+#define DBGWCR_LBN_SHIFT 16
+#define DBGWCR_LBN (0xf << DBGWCR_LBN_SHIFT)
+#define DBGWCR_WT_SHIFT 20
+#define DBGWCR_WT (0x1 << DBGWCR_WT_SHIFT)
+#define DBGWCR_MASK_SHIFT 24
+#define DBGWCR_MASK (0x1f << DBGWCR_MASK_SHIFT)
+
/* DCZID_EL0 - Data Cache Zero ID register */
#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
#define DCZID_BS_SHIFT 0
@@ -1059,6 +1097,14 @@
#define MAIR_NORMAL_WT 0xbb
#define MAIR_NORMAL_WB 0xff
+/* MDSCR_EL1 - Monitor Debug System Control Register */
+#define MDSCR_SS_SHIFT 0
+#define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT)
+#define MDSCR_KDE_SHIFT 13
+#define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT)
+#define MDSCR_MDE_SHIFT 15
+#define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT)
+
/* MVFR0_EL1 */
#define MVFR0_EL1 MRS_REG(MVFR0_EL1)
#define MVFR0_EL1_op0 0x3
@@ -1381,52 +1427,6 @@
#define TTBR_CnP_SHIFT 0
#define TTBR_CnP (1ul << TTBR_CnP_SHIFT)
-/* Saved Program Status Register */
-#define DBG_SPSR_SS (0x1 << 21)
-
-/* Monitor Debug System Control Register */
-#define DBG_MDSCR_SS (0x1 << 0)
-#define DBG_MDSCR_KDE (0x1 << 13)
-#define DBG_MDSCR_MDE (0x1 << 15)
-
-/* Debug Breakpoint Control Registers */
-#define DBG_BCR_EN 0x1
-#define DBG_BCR_PMC_SHIFT 1
-#define DBG_BCR_PMC (0x3 << DBG_BCR_PMC_SHIFT)
-#define DBG_BCR_PMC_EL1 (0x1 << DBG_BCR_PMC_SHIFT)
-#define DBG_BCR_PMC_EL0 (0x2 << DBG_BCR_PMC_SHIFT)
-#define DBG_BCR_BAS_SHIFT 5
-#define DBG_BCR_BAS (0xf << DBG_BCR_BAS_SHIFT)
-#define DBG_BCR_HMC_SHIFT 13
-#define DBG_BCR_HMC (0x1 << DBG_BCR_HMC_SHIFT)
-#define DBG_BCR_SSC_SHIFT 14
-#define DBG_BCR_SSC (0x3 << DBG_BCR_SSC_SHIFT)
-#define DBG_BCR_LBN_SHIFT 16
-#define DBG_BCR_LBN (0xf << DBG_BCR_LBN_SHIFT)
-#define DBG_BCR_BT_SHIFT 20
-#define DBG_BCR_BT (0xf << DBG_BCR_BT_SHIFT)
-
-/* Debug Watchpoint Control Registers */
-#define DBG_WCR_EN 0x1
-#define DBG_WCR_PAC_SHIFT 1
-#define DBG_WCR_PAC (0x3 << DBG_WCR_PAC_SHIFT)
-#define DBG_WCR_PAC_EL1 (0x1 << DBG_WCR_PAC_SHIFT)
-#define DBG_WCR_PAC_EL0 (0x2 << DBG_WCR_PAC_SHIFT)
-#define DBG_WCR_LSC_SHIFT 3
-#define DBG_WCR_LSC (0x3 << DBG_WCR_LSC_SHIFT)
-#define DBG_WCR_BAS_SHIFT 5
-#define DBG_WCR_BAS (0xff << DBG_WCR_BAS_SHIFT)
-#define DBG_WCR_BAS_MASK DBG_WCR_BAS
-#define DBG_WCR_HMC_SHIFT 13
-#define DBG_WCR_HMC (0x1 << DBG_WCR_HMC_SHIFT)
-#define DBG_WCR_SSC_SHIFT 14
-#define DBG_WCR_SSC (0x3 << DBG_WCR_SSC_SHIFT)
-#define DBG_WCR_LBN_SHIFT 16
-#define DBG_WCR_LBN (0xf << DBG_WCR_LBN_SHIFT)
-#define DBG_WCR_WT_SHIFT 20
-#define DBG_WCR_WT (0x1 << DBG_WCR_WT_SHIFT)
-#define DBG_WCR_MASK_SHIFT 24
-#define DBG_WCR_MASK (0x1f << DBG_WCR_MASK_SHIFT)
/* Perfomance Monitoring Counters */
#define PMCR_E (1 << 0) /* Enable all counters */

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