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diff --git a/sys/dev/ufshci/ufshci_dev.c b/sys/dev/ufshci/ufshci_dev.c
--- a/sys/dev/ufshci/ufshci_dev.c
+++ b/sys/dev/ufshci/ufshci_dev.c
@@ -325,7 +325,7 @@
*/
const uint32_t fast_mode = 1;
const uint32_t rx_bit_shift = 4;
- uint32_t power_mode, peer_granularity;
+ uint32_t peer_granularity;
/* Update lanes with available TX/RX lanes */
if (ufshci_uic_send_dme_get(ctrlr, PA_AvailTxDataLanes,
@@ -352,9 +352,11 @@
if (ctrlr->quirks & UFSHCI_QUIRK_CHANGE_LANE_AND_GEAR_SEPARATELY) {
/* Before changing gears, first change the number of lanes. */
- if (ufshci_uic_send_dme_get(ctrlr, PA_PWRMode, &power_mode))
+ if (ufshci_uic_send_dme_get(ctrlr, PA_PWRMode,
+ &ctrlr->tx_rx_power_mode))
return (ENXIO);
- if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, power_mode))
+ if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode,
+ ctrlr->tx_rx_power_mode))
return (ENXIO);
/* Wait for power mode changed. */
@@ -415,8 +417,8 @@
return (ENXIO);
/* Set TX/RX PWRMode */
- power_mode = (fast_mode << rx_bit_shift) | fast_mode;
- if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, power_mode))
+ ctrlr->tx_rx_power_mode = (fast_mode << rx_bit_shift) | fast_mode;
+ if (ufshci_uic_send_dme_set(ctrlr, PA_PWRMode, ctrlr->tx_rx_power_mode))
return (ENXIO);
/* Wait for power mode changed. */
diff --git a/sys/dev/ufshci/ufshci_pci.c b/sys/dev/ufshci/ufshci_pci.c
--- a/sys/dev/ufshci/ufshci_pci.c
+++ b/sys/dev/ufshci/ufshci_pci.c
@@ -34,8 +34,7 @@
DEVMETHOD(device_attach, ufshci_pci_attach),
DEVMETHOD(device_detach, ufshci_pci_detach),
DEVMETHOD(device_suspend, ufshci_pci_suspend),
- DEVMETHOD(device_resume, ufshci_pci_resume),
- DEVMETHOD_END
+ DEVMETHOD(device_resume, ufshci_pci_resume), DEVMETHOD_END
};
static driver_t ufshci_pci_driver = {
diff --git a/sys/dev/ufshci/ufshci_private.h b/sys/dev/ufshci/ufshci_private.h
--- a/sys/dev/ufshci/ufshci_private.h
+++ b/sys/dev/ufshci/ufshci_private.h
@@ -396,7 +396,8 @@
/* UFS Interconnect Layer (UIC) */
struct mtx uic_cmd_lock;
- uint8_t hs_gear;
+ uint32_t tx_rx_power_mode;
+ uint32_t hs_gear;
uint32_t tx_lanes;
uint32_t rx_lanes;
uint32_t max_rx_hs_gear;
diff --git a/sys/dev/ufshci/ufshci_sysctl.c b/sys/dev/ufshci/ufshci_sysctl.c
--- a/sys/dev/ufshci/ufshci_sysctl.c
+++ b/sys/dev/ufshci/ufshci_sysctl.c
@@ -232,6 +232,31 @@
SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "power_mode",
CTLFLAG_RD, &dev->power_mode, 0, "Current device power mode");
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "tx_rx_power_mode",
+ CTLFLAG_RD, &ctrlr->tx_rx_power_mode, 0,
+ "Current TX/RX PA_PWRMode value");
+
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "max_tx_lanes",
+ CTLFLAG_RD, &ctrlr->max_tx_lanes, 0,
+ "Maximum available TX data lanes");
+
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "max_rx_lanes",
+ CTLFLAG_RD, &ctrlr->max_rx_lanes, 0,
+ "Maximum available RX data lanes");
+
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "tx_lanes", CTLFLAG_RD,
+ &ctrlr->tx_lanes, 0, "Active TX data lanes");
+
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "rx_lanes", CTLFLAG_RD,
+ &ctrlr->rx_lanes, 0, "Active RX data lanes");
+
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "max_rx_hs_gear",
+ CTLFLAG_RD, &ctrlr->max_rx_hs_gear, 0,
+ "Maximum available RX HS gear");
+
+ SYSCTL_ADD_UINT(ctrlr_ctx, ctrlr_list, OID_AUTO, "hs_gear", CTLFLAG_RD,
+ &ctrlr->hs_gear, 0, "Active HS gear");
+
SYSCTL_ADD_PROC(ctrlr_ctx, ctrlr_list, OID_AUTO, "timeout_period",
CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, &ctrlr->timeout_period,
0, ufshci_sysctl_timeout_period, "IU",

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