D4113.id10053.diff
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	Index: sys/arm/include/atomic-v6.h
	===================================================================
	--- sys/arm/include/atomic-v6.h
	+++ sys/arm/include/atomic-v6.h
	@@ -593,6 +593,60 @@
	*p = v;
	}

	+static __inline int
	+atomic_testandset_32(volatile uint32_t *p, u_int v)
	+{
	+ uint32_t tmp, tmp2, res, mask;
	+
	+ mask = 1u << (v & 0x1f);
	+ tmp = tmp2 = 0;
	+ __asm __volatile(
	+ "1: ldrex %0, [%3] \n"
	+ " orr %1, %0, %4 \n"
	+ " strex %2, %1, [%3] \n"
	+ " cmp %2, #0 \n"
	+ " it ne \n"
	+ " bne 1b \n"
	+ : "=&r" (res), "=&r" (tmp), "=&r" (tmp2), "+&r" (p)
	+ : "r" (mask)
	+ : "cc", "memory");
	+ return ((res & mask) != 0);
	+}
	+
	+static __inline int
	+atomic_testandset_int(volatile u_int *p, u_int v)
	+{
	+
	+ return (atomic_testandset_32((volatile uint32_t *)p, v));
	+}
	+
	+static __inline int
	+atomic_testandset_long(volatile u_long *p, u_int v)
	+{
	+
	+ return (atomic_testandset_32((volatile uint32_t *)p, v));
	+}
	+
	+static __inline int
	+atomic_testandset_64(volatile uint64_t *p, u_int v)
	+{
	+ volatile uint32_t *p32;
	+
	+ p32 = (volatile uint32_t *)p;
	+#if BYTE_ORDER == LITTLE_ENDIAN
	+ if (v >= 32) {
	+ v &= 0x1f;
	+ p32++;
	+ }
	+#else
	+ if (v >= 32)
	+ v &= 0x1f;
	+ else
	+ p32++;
	+#endif
	+ return (atomic_testandset_32(p32, v));
	+}
	+
	#undef ATOMIC_ACQ_REL
	#undef ATOMIC_ACQ_REL_LONG