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D55975.id174361.diff
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D55975.id174361.diff

diff --git a/lib/msun/aarch64/fenv.h b/lib/msun/aarch64/fenv.h
--- a/lib/msun/aarch64/fenv.h
+++ b/lib/msun/aarch64/fenv.h
@@ -81,8 +81,11 @@
#define __mrs_fpsr(__r) __asm __volatile("mrs %0, fpsr" : "=r" (__r))
#define __msr_fpsr(__r) __asm __volatile("msr fpsr, %0" : : "r" (__r))
-__fenv_static __inline int
-feclearexcept(int __excepts)
+int feclearexcept(int);
+#define feclearexcept(a) __feclearexcept_int(a)
+
+__fenv_static inline int
+__feclearexcept_int(int __excepts)
{
fexcept_t __r;
diff --git a/lib/msun/aarch64/fenv.c b/lib/msun/aarch64/fenv.c
--- a/lib/msun/aarch64/fenv.c
+++ b/lib/msun/aarch64/fenv.c
@@ -38,7 +38,12 @@
#error "This file must be compiled with C99 'inline' semantics"
#endif
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+ return (__feclearexcept_int(excepts));
+}
+
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/amd64/fenv.c b/lib/msun/amd64/fenv.c
--- a/lib/msun/amd64/fenv.c
+++ b/lib/msun/amd64/fenv.c
@@ -46,7 +46,12 @@
__INITIAL_MXCSR__
};
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+ return (__feclearexcept_int(excepts));
+}
+
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
int
diff --git a/lib/msun/arm/fenv.h b/lib/msun/arm/fenv.h
--- a/lib/msun/arm/fenv.h
+++ b/lib/msun/arm/fenv.h
@@ -111,8 +111,11 @@
#define _FPU_MASK_SHIFT 8
+int feclearexcept(int);
+#define feclearexcept(a) __feclearexcept_int(a)
+
__fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
{
fexcept_t __fpsr;
diff --git a/lib/msun/arm/fenv.c b/lib/msun/arm/fenv.c
--- a/lib/msun/arm/fenv.c
+++ b/lib/msun/arm/fenv.c
@@ -70,7 +70,12 @@
#error "This file must be compiled with C99 'inline' semantics"
#endif
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+ return (__feclearexcept_int(excepts));
+}
+
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/i387/fenv.c b/lib/msun/i387/fenv.c
--- a/lib/msun/i387/fenv.c
+++ b/lib/msun/i387/fenv.c
@@ -88,7 +88,12 @@
return (0);
}
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+ return (__feclearexcept_int(excepts));
+}
+
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
int
diff --git a/lib/msun/powerpc/fenv.h b/lib/msun/powerpc/fenv.h
--- a/lib/msun/powerpc/fenv.h
+++ b/lib/msun/powerpc/fenv.h
@@ -111,8 +111,11 @@
} __bits;
};
+int feclearexcept(int);
+#define feclearexcept(a) __feclearexcept_int(a)
+
__fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
{
union __fpscr __r;
diff --git a/lib/msun/powerpc/fenv.c b/lib/msun/powerpc/fenv.c
--- a/lib/msun/powerpc/fenv.c
+++ b/lib/msun/powerpc/fenv.c
@@ -35,7 +35,12 @@
const fenv_t __fe_dfl_env = 0x00000000;
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+ return (__feclearexcept_int(excepts));
+}
+
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/riscv/fenv.h b/lib/msun/riscv/fenv.h
--- a/lib/msun/riscv/fenv.h
+++ b/lib/msun/riscv/fenv.h
@@ -79,8 +79,11 @@
#define __rfs(__fcsr) __asm __volatile("csrr %0, fcsr" : "=r" (__fcsr))
#define __wfs(__fcsr) __asm __volatile("csrw fcsr, %0" :: "r" (__fcsr))
+int feclearexcept(int);
+#define feclearexcept(a) __feclearexcept_int(a)
+
__fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
{
__asm __volatile("csrc fflags, %0" :: "r"(__excepts));
diff --git a/lib/msun/riscv/fenv.c b/lib/msun/riscv/fenv.c
--- a/lib/msun/riscv/fenv.c
+++ b/lib/msun/riscv/fenv.c
@@ -37,7 +37,12 @@
*/
const fenv_t __fe_dfl_env = 0;
-extern inline int feclearexcept(int __excepts);
+int
+(feclearexcept)(int excepts)
+{
+ return (__feclearexcept_int(excepts));
+}
+
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
extern inline int feraiseexcept(int __excepts);
diff --git a/lib/msun/x86/fenv.h b/lib/msun/x86/fenv.h
--- a/lib/msun/x86/fenv.h
+++ b/lib/msun/x86/fenv.h
@@ -143,6 +143,9 @@
#endif /* __BSD_VISIBLE */
+int feclearexcept(int);
+#define feclearexcept(a) __feclearexcept_int(a)
+
#ifdef __i386__
/* After testing for SSE support once, we cache the result in __has_sse. */
@@ -164,7 +167,7 @@
} while (0)
__fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
{
fenv_t __env;
__uint32_t __mxcsr;
@@ -262,7 +265,7 @@
#else /* __amd64__ */
__fenv_static inline int
-feclearexcept(int __excepts)
+__feclearexcept_int(int __excepts)
{
fenv_t __env;

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