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Index: sys/arm64/arm64/exception.S
===================================================================
--- sys/arm64/arm64/exception.S
+++ sys/arm64/arm64/exception.S
@@ -78,7 +78,9 @@
ldr x0, [x18, #(PC_CURTHREAD)]
bl dbg_monitor_enter
- msr daifclr, #DAIF_D /* Enable the debug exception */
+
+ /* Unmask debug and SError exceptions */
+ msr daifclr, #(DAIF_D | DAIF_A)
.endif
/*
* For EL1, debug exceptions are conditionally unmasked in
@@ -87,14 +89,11 @@
.endm
.macro restore_registers el
-.if \el == 1
/*
- * Disable interrupts and debug exceptions, x18 may change in the
- * interrupt exception handler. For EL0 exceptions, do_ast already
- * did this.
+ * Mask all exceptions, x18 may change in the interrupt exception
+ * handler.
*/
- msr daifset, #(DAIF_D | DAIF_INTR)
-.endif
+ msr daifset, #(DAIF_ALL)
.if \el == 0
ldr x0, [x18, #PC_CURTHREAD]
mov x1, sp
@@ -153,8 +152,10 @@
/* Make sure the IRQs are enabled before calling ast() */
bic x19, x19, #PSR_I
1:
- /* Disable interrupts */
- msr daifset, #(DAIF_D | DAIF_INTR)
+ /*
+ * Mask interrupts while checking the ast pending flag
+ */
+ msr daifset, #(DAIF_INTR)
/* Read the current thread flags */
ldr x1, [x18, #PC_CURTHREAD] /* Load curthread */
Index: sys/arm64/arm64/machdep.c
===================================================================
--- sys/arm64/arm64/machdep.c
+++ sys/arm64/arm64/machdep.c
@@ -935,6 +935,12 @@
thread0.td_frame = &proc0_tf;
ptrauth_thread0(&thread0);
pcpup->pc_curpcb = thread0.td_pcb;
+
+ /*
+ * Unmask SError exceptions. They are used to signal a RAS failure,
+ * or other hardware error.
+ */
+ __asm __volatile("msr daifclr, #(" __XSTRING(DAIF_A) ")");
}
typedef struct {
Index: sys/arm64/arm64/vm_machdep.c
===================================================================
--- sys/arm64/arm64/vm_machdep.c
+++ sys/arm64/arm64/vm_machdep.c
@@ -114,7 +114,7 @@
/* Setup to release spin count in fork_exit(). */
td2->td_md.md_spinlock_count = 1;
- td2->td_md.md_saved_daif = td1->td_md.md_saved_daif & ~DAIF_I_MASKED;
+ td2->td_md.md_saved_daif = PSR_DAIF_DEFAULT;
}
void
@@ -188,7 +188,7 @@
/* Setup to release spin count in fork_exit(). */
td->td_md.md_spinlock_count = 1;
- td->td_md.md_saved_daif = td0->td_md.md_saved_daif & ~DAIF_I_MASKED;
+ td->td_md.md_saved_daif = PSR_DAIF_DEFAULT;
/* Generate new pointer authentication keys. */
ptrauth_copy_thread(td, td0);
Index: sys/arm64/include/armreg.h
===================================================================
--- sys/arm64/include/armreg.h
+++ sys/arm64/include/armreg.h
@@ -124,12 +124,6 @@
#define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK)
#define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
-/* DAIF - Interrupt Mask Bits */
-#define DAIF_D_MASKED (1 << 9)
-#define DAIF_A_MASKED (1 << 8)
-#define DAIF_I_MASKED (1 << 7)
-#define DAIF_F_MASKED (1 << 6)
-
/* DAIFSet/DAIFClear */
#define DAIF_D (1 << 3)
#define DAIF_A (1 << 2)
@@ -1079,6 +1073,8 @@
#define PSR_A 0x00000100
#define PSR_D 0x00000200
#define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F)
+/* The default DAIF mask. These bits are valid in spsr_el1 and daif */
+#define PSR_DAIF_DEFAULT (PSR_F)
#define PSR_IL 0x00100000
#define PSR_SS 0x00200000
#define PSR_V 0x10000000

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