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Index: sys/arm64/conf/std.rockchip
===================================================================
--- sys/arm64/conf/std.rockchip
+++ sys/arm64/conf/std.rockchip
@@ -3,6 +3,7 @@
#
# SoC support
+options SOC_ROCKCHIP_RK3308
options SOC_ROCKCHIP_RK3328
options SOC_ROCKCHIP_RK3399
options SOC_ROCKCHIP_RK3568
Index: sys/arm64/rockchip/clk/rk3308_cru.c
===================================================================
--- /dev/null
+++ sys/arm64/rockchip/clk/rk3308_cru.c
@@ -0,0 +1,749 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Titus Manea <titus@edc.ro>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <machine/bus.h>
+
+#include <dev/fdt/simplebus.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/extres/clk/clk_div.h>
+#include <dev/extres/clk/clk_fixed.h>
+#include <dev/extres/clk/clk_mux.h>
+
+#include <arm64/rockchip/clk/rk_cru.h>
+#include <contrib/device-tree/include/dt-bindings/clock/rk3308-cru.h>
+
+
+#define RK3308_PLLSEL_CON(x) ((x) * 0x20)
+#define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
+#define RK3308_GLB_SRST_FST 0xb8
+#define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
+#define RK3308_MODE_CON 0xa0
+#define RK3308_SDMMC_CON0 0x480
+#define RK3308_SDMMC_CON1 0x484
+#define RK3308_SDIO_CON0 0x488
+#define RK3308_SDIO_CON1 0x48c
+#define RK3308_EMMC_CON0 0x490
+#define RK3308_EMMC_CON1 0x494
+
+
+#define PNAME(_name) static const char *_name[]
+
+
+#define RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd) \
+{ \
+ .freq = _hz, \
+ .refdiv = _ref, \
+ .fbdiv = _fb, \
+ .postdiv1 = _post1, \
+ .postdiv2 = _post2, \
+ .dsmpd = _dspd, \
+}
+
+/* PLL clock */
+#define RK_PLL(_id, _name, _pnames, _off, _shift) \
+{ \
+ .type = RK3328_CLK_PLL, \
+ .clk.pll = &(struct rk_clk_pll_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = _pnames, \
+ .clkdef.parent_cnt = nitems(_pnames), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .base_offset = RK3308_PLLSEL_CON(_off), \
+ .mode_reg = 0xc0, \
+ .mode_shift = _shift, \
+ .rates = rk3308_pll_rates, \
+ }, \
+}
+
+/* Clock for ARM core(s) */
+#define RK_ARMDIV(_id, _nm, _pn, _r, _off, _ds, _dw, _ms, _mw, _mp, _ap)\
+{ \
+ .type = RK_CLK_ARMCLK, \
+ .clk.armclk = &(struct rk_clk_armclk_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _nm, \
+ .clkdef.parent_names = _pn, \
+ .clkdef.parent_cnt = nitems(_pn), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .muxdiv_offset = RK3308_CLKSEL_CON(_off), \
+ .mux_shift = _ms, \
+ .mux_width = _mw, \
+ .div_shift = _ds, \
+ .div_width = _dw, \
+ .main_parent = _mp, \
+ .alt_parent = _ap, \
+ .rates = _r, \
+ .nrates = nitems(_r), \
+ }, \
+}
+
+/* Composite */
+#define RK_COMPOSITE(_id, _name, _pnames, _o, _ms, _mw, _ds, _dw, _go, _gw,_f)\
+{ \
+ .type = RK_CLK_COMPOSITE, \
+ .clk.composite = &(struct rk_clk_composite_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = _pnames, \
+ .clkdef.parent_cnt = nitems(_pnames), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .muxdiv_offset = RK3308_CLKSEL_CON(_o), \
+ .mux_shift = _ms, \
+ .mux_width = _mw, \
+ .div_shift = _ds, \
+ .div_width = _dw, \
+ .gate_offset = RK3308_CLKGATE_CON(_go), \
+ .gate_shift = _gw, \
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | \
+ RK_CLK_COMPOSITE_HAVE_GATE | _f, \
+ }, \
+}
+
+/* Composite no mux */
+#define RK_COMPNOMUX(_id, _name, _pname, _o, _ds, _dw, _go, _gw, _f) \
+{ \
+ .type = RK_CLK_COMPOSITE, \
+ .clk.composite = &(struct rk_clk_composite_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = (const char *[]){_pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .muxdiv_offset = RK3308_CLKSEL_CON(_o), \
+ .div_shift = _ds, \
+ .div_width = _dw, \
+ .gate_offset = RK3308_CLKGATE_CON(_go), \
+ .gate_shift = _gw, \
+ .flags = RK_CLK_COMPOSITE_HAVE_GATE | _f, \
+ }, \
+}
+
+/* Composite no div */
+#define RK_COMPNODIV(_id, _name, _pnames, _o, _ms, _mw, _go, _gw, _f) \
+{ \
+ .type = RK_CLK_COMPOSITE, \
+ .clk.composite = &(struct rk_clk_composite_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = _pnames, \
+ .clkdef.parent_cnt = nitems(_pnames), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .muxdiv_offset = RK3308_CLKSEL_CON(_o), \
+ .mux_shift = _ms, \
+ .mux_width = _mw, \
+ .gate_offset = RK3308_CLKGATE_CON(_go), \
+ .gate_shift = _gw, \
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | \
+ RK_CLK_COMPOSITE_HAVE_GATE | _f, \
+ }, \
+}
+
+/* Composite div only */
+#define RK_COMPDIV(_id, _name, _pname, _o, _ds, _dw, _f) \
+{ \
+ .type = RK_CLK_COMPOSITE, \
+ .clk.composite = &(struct rk_clk_composite_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = (const char *[]){_pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .muxdiv_offset = RK3308_CLKSEL_CON(_o), \
+ .div_shift = _ds, \
+ .div_width = _dw, \
+ .flags = _f, \
+ }, \
+}
+
+
+/* Fixed factor mux/div */
+#define RK_FACTOR(_id, _name, _pname, _mult, _div) \
+{ \
+ .type = RK_CLK_FIXED, \
+ .clk.fixed = &(struct clk_fixed_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = (const char *[]){_pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .mult = _mult, \
+ .div = _div, \
+ }, \
+}
+
+
+#define RK_FACTOR_GATE(_id, cname, pname,f, fm, fd, go, gb, gf) \
+ { \
+ .type = RK_CLK_COMPOSITE, \
+ .clk.composite = &(struct rk_clk_composite_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){ pname }, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .div_shift = fm, \
+ .div_width = fd, \
+ .gate_offset = go, \
+ .gate_shift = gb, \
+ .flags = RK_CLK_FRACT_HAVE_GATE | gf, \
+ }, \
+}
+/* Fractional */
+#define RK_FRACTION(_id, _name, _pname, _o, _go, _gw, _f) \
+{ \
+ .type = RK_CLK_FRACT, \
+ .clk.fract = &(struct rk_clk_fract_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = (const char *[]){_pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = RK3308_CLKSEL_CON(_o), \
+ .gate_offset = RK3308_CLKGATE_CON(_go), \
+ .gate_shift = _gw, \
+ .flags = RK_CLK_FRACT_HAVE_GATE | _f, \
+ }, \
+}
+
+/* Multiplexer */
+#define RK_MUX(_id, _name, _pnames, _o, _ms, _mw, _f) \
+{ \
+ .type = RK_CLK_MUX, \
+ .clk.mux = &(struct rk_clk_mux_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = _pnames, \
+ .clkdef.parent_cnt = nitems(_pnames), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = RK3308_CLKSEL_CON(_o), \
+ .shift = _ms, \
+ .width = _mw, \
+ .mux_flags = _f, \
+ }, \
+}
+
+#define RK_GATE(_id, _name, _pname, _o, _s) \
+{ \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .offset = RK3308_CLKGATE_CON(_o), \
+ .shift = _s, \
+}
+#define RK_MMC(_id, _name, _pname, _o, _ds) \
+{ \
+ .type = RK_CLK_COMPOSITE, \
+ .clk.composite = &(struct rk_clk_composite_def) { \
+ .clkdef.id = _id, \
+ .clkdef.name = _name, \
+ .clkdef.parent_names = (const char *[]){_pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .muxdiv_offset = RK3308_CLKSEL_CON(_o), \
+ .div_shift = _ds, \
+ }, \
+}
+
+struct rk_clk_pll_rate rk3308_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */
+ RK_PLLRATE(1608000000, 1, 67, 1, 1, 1),
+ RK_PLLRATE(1584000000, 1, 66, 1, 1, 1),
+ RK_PLLRATE(1560000000, 1, 65, 1, 1, 1),
+ RK_PLLRATE(1536000000, 1, 64, 1, 1, 1),
+ RK_PLLRATE(1512000000, 1, 63, 1, 1, 1),
+ RK_PLLRATE(1488000000, 1, 62, 1, 1, 1),
+ RK_PLLRATE(1464000000, 1, 61, 1, 1, 1),
+ RK_PLLRATE(1440000000, 1, 60, 1, 1, 1),
+ RK_PLLRATE(1416000000, 1, 59, 1, 1, 1),
+ RK_PLLRATE(1392000000, 1, 58, 1, 1, 1),
+ RK_PLLRATE(1368000000, 1, 57, 1, 1, 1),
+ RK_PLLRATE(1344000000, 1, 56, 1, 1, 1),
+ RK_PLLRATE(1320000000, 1, 55, 1, 1, 1),
+ RK_PLLRATE(1296000000, 1, 54, 1, 1, 1),
+ RK_PLLRATE(1272000000, 1, 53, 1, 1, 1),
+ RK_PLLRATE(1248000000, 1, 52, 1, 1, 1),
+ RK_PLLRATE(1200000000, 1, 50, 1, 1, 1),
+ RK_PLLRATE(1188000000, 2, 99, 1, 1, 1),
+ RK_PLLRATE(1104000000, 1, 46, 1, 1, 1),
+ RK_PLLRATE(1100000000, 12, 550, 1, 1, 1),
+ RK_PLLRATE(1008000000, 1, 84, 2, 1, 1),
+ RK_PLLRATE(1000000000, 6, 500, 2, 1, 1),
+ RK_PLLRATE(984000000, 1, 82, 2, 1, 1),
+ RK_PLLRATE(960000000, 1, 80, 2, 1, 1),
+ RK_PLLRATE(936000000, 1, 78, 2, 1, 1),
+ RK_PLLRATE(912000000, 1, 76, 2, 1, 1),
+ RK_PLLRATE(900000000, 4, 300, 2, 1, 1),
+ RK_PLLRATE(888000000, 1, 74, 2, 1, 1),
+ RK_PLLRATE(864000000, 1, 72, 2, 1, 1),
+ RK_PLLRATE(840000000, 1, 70, 2, 1, 1),
+ RK_PLLRATE(816000000, 1, 68, 2, 1, 1),
+ RK_PLLRATE(800000000, 6, 400, 2, 1, 1),
+ RK_PLLRATE(700000000, 6, 350, 2, 1, 1),
+ RK_PLLRATE(696000000, 1, 58, 2, 1, 1),
+ RK_PLLRATE(624000000, 1, 52, 2, 1, 1),
+ RK_PLLRATE(600000000, 1, 75, 3, 1, 1),
+ RK_PLLRATE(594000000, 2, 99, 2, 1, 1),
+ RK_PLLRATE(504000000, 1, 63, 3, 1, 1),
+ RK_PLLRATE(500000000, 6, 250, 2, 1, 1),
+ RK_PLLRATE(408000000, 1, 68, 2, 2, 1),
+ RK_PLLRATE(312000000, 1, 52, 2, 2, 1),
+ RK_PLLRATE(216000000, 1, 72, 4, 2, 1),
+ RK_PLLRATE(96000000, 1, 64, 4, 4, 1),
+ { /* sentinel */ },
+};
+
+static struct rk_clk_armclk_rates rk3308_armclk_rates[] = {
+ {1608000000, 1},
+ {1512000000, 1},
+ {1488000000, 1},
+ {1416000000, 1},
+ {1392000000, 1},
+ {1296000000, 1},
+ {1200000000, 1},
+ {1104000000, 1},
+ {1008000000, 1},
+ {912000000, 1},
+ {816000000, 1},
+ {696000000, 1},
+ {600000000, 1},
+ {408000000, 1},
+ {312000000, 1},
+ {216000000, 1},
+ {96000000, 1},
+ {},
+};
+
+/* Parent clock defines */
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
+PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
+PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
+PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
+PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
+PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
+PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
+PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
+PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
+PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" };
+PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
+PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
+PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
+PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
+PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
+PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
+PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
+PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
+PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
+PNAME(mux_mac_p) = { "clk_mac_src", "mac_clkin" };
+PNAME(mux_mac_rmii_sel_p) = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" };
+PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" };
+PNAME(mux_rtc32k_p) = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" };
+PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
+PNAME(mux_wifi_src_p) = { "clk_wifi_dpll", "clk_wifi_vpll0" };
+PNAME(mux_wifi_p) = { "clk_wifi_osc", "clk_wifi_src" };
+PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
+PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" };
+PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
+PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m" };
+PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" };
+PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
+PNAME(mux_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" };
+PNAME(mux_i2s1_8ch_tx_rx_p) = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"};
+PNAME(mux_i2s1_8ch_tx_out_p) = { "clk_i2s1_8ch_tx", "xin12m" };
+PNAME(mux_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" };
+PNAME(mux_i2s1_8ch_rx_tx_p) = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"};
+PNAME(mux_i2s2_8ch_tx_p) = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" };
+PNAME(mux_i2s2_8ch_tx_rx_p) = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"};
+PNAME(mux_i2s2_8ch_tx_out_p) = { "clk_i2s2_8ch_tx", "xin12m" };
+PNAME(mux_i2s2_8ch_rx_p) = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" };
+PNAME(mux_i2s2_8ch_rx_tx_p) = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"};
+PNAME(mux_i2s3_8ch_tx_p) = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" };
+PNAME(mux_i2s3_8ch_tx_rx_p) = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"};
+PNAME(mux_i2s3_8ch_tx_out_p) = { "clk_i2s3_8ch_tx", "xin12m" };
+PNAME(mux_i2s3_8ch_rx_p) = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" };
+PNAME(mux_i2s3_8ch_rx_tx_p) = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"};
+PNAME(mux_i2s0_2ch_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" };
+PNAME(mux_i2s0_2ch_out_p) = { "clk_i2s0_2ch", "xin12m" };
+PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"};
+PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
+PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
+PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
+PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
+PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
+/* CLOCKS */
+static struct rk_clk rk3308_clks[] = {
+ /* External clocks */
+ LINK("xin24m"),
+ LINK("clk_rtc_32k"),
+ LINK("usb480m_phy"),
+// LINK("jtag_clkin"),
+ LINK("clk_ddrphy1x_out"),
+ LINK("clk_pvtm_32k"),
+ LINK("xin32k"),
+ LINK("mclk_i2s0_8ch_in"),
+ LINK("mclk_i2s1_8ch_in"), // SOS SCRU
+ LINK("mclk_i2s2_8ch_in"),
+ LINK("mclk_i2s3_8ch_in"),
+ LINK("mclk_i2s0_2ch_in"),
+ LINK("mclk_i2s1_2ch_in"),
+ LINK("mac_clkin"),
+ LINK("dummy"),
+ /* PLL's */
+ RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0),
+ RK_PLL(PLL_DPLL, "dpll", mux_pll_p, 1, 2),
+ RK_PLL(PLL_VPLL0, "vpll0", mux_pll_p, 2, 4),
+ RK_PLL(PLL_VPLL1, "vpll1", mux_pll_p, 3, 6),
+ RK_ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3308_armclk_rates, 0, 0, 5,6, 1, 0, 1),
+ RK_MUX(USB480M, "usb480m", mux_usb480m_p, RK3308_MODE_CON, 8, 2, 0),
+ RK_FACTOR(0, "xin12m", "xin24m", 1, 2),
+ RK_COMPNOMUX(0, "pclk_core_dbg", "armclk", 0, 8, 4, 0, 2, 0),
+ RK_COMPNOMUX(0, "aclk_core", "armclk", 0, 12, 3, 0, 1, 0),
+ RK_COMPNODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, 5, 6, 2, 1, 0, 0),
+ RK_COMPNOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", 6, 8, 5, 1, 3, 0),
+ RK_COMPNOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", 6, 0, 5, 1, 2, 0),
+ RK_COMPNOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", 5, 0, 5, 1, 1, 0),
+ RK_COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 10, 13, 3, 0, 5, 1, 9, 0),
+ RK_FRACTION(0, "clk_uart0_frac", "clk_uart0_src", 12, 1, 11, 0),
+ RK_MUX(0, "clk_uart0_mux", mux_uart0_p, 11, 14, 2, 0),
+ RK_COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 13, 13, 3, 0, 5, 1, 13, 0),
+ RK_FRACTION(0, "clk_uart1_frac", "clk_uart1_src", 15, 1, 15, 0),
+ RK_MUX(0, "clk_uart1_mux", mux_uart1_p, 14, 14, 2, 0),
+ RK_COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 16, 13, 3, 0, 5, 2, 1, 0),
+ RK_FRACTION(0, "clk_uart2_frac", "clk_uart2_src", 18, 2, 3, 0),
+ RK_MUX(0, "clk_uart2_mux", mux_uart2_p, 17, 14, 2, 0),
+ RK_COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 19, 13, 3, 0, 5, 2, 5, 0),
+ RK_FRACTION(0, "clk_uart3_frac", "clk_uart3_src", 21, 2, 7, 0),
+ RK_MUX(0, "clk_uart3_mux", mux_uart3_p, 20, 14, 2, 0),
+ RK_COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 22, 13, 3, 0, 5, 2, 9, 0),
+ RK_FRACTION(0, "clk_uart4_frac", "clk_uart4_src", 24, 2, 11, 0),
+ RK_MUX(0, "clk_uart4_mux", mux_uart4_p, 23, 14, 2, 0),
+ RK_COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 25, 14, 2, 0, 7, 2, 13, 0),
+ RK_COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 26, 14, 2, 0, 7, 2, 14, 0),
+ RK_COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 27, 14, 2, 0, 7, 2, 15, 0),
+ RK_COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 28, 14, 2, 0, 7, 3, 0, 0),
+ RK_COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 29, 14, 2, 0, 7, 3, 1, 0),
+ RK_COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 74, 14, 2, 0, 7, 15, 0, 0),
+ RK_COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 75, 14, 2, 0, 7, 15, 1, 0),
+ RK_COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 30, 14, 2, 0, 7, 3, 2, 0),
+ RK_COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 31, 14, 2, 0, 7, 3, 3, 0),
+ RK_COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 32, 14, 2, 0, 7, 3, 4, 0),
+ RK_COMPNOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 33, 0, 11, 3, 5, 0),
+ RK_COMPNOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 34, 0, 11, 3, 6, 0),
+ RK_COMPNOMUX(SCLK_OTP, "clk_otp", "xin24m", 35, 0, 4, 3, 7, 0),
+ RK_COMPNOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 35, 4, 2, 3, 8, 0),
+ RK_COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 7, 6, 2, 0, 5, 1, 4, 0),
+ RK_COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 7, 14, 2, 8, 5, 1, 5, 0),
+ RK_COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 8, 10, 2, 0, 8, 1, 6, 0),
+ RK_FRACTION(0, "dclk_vop_frac", "dclk_vop_src", 9, 1, 7, 0),
+ RK_MUX(0, "dclk_vop_mux", mux_dclk_vop_p, 8, 14, 2, 0),
+ RK_COMPNODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, 36, 6, 2, 8, 0, 0),
+ RK_COMPNOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", 36, 0, 5, 8, 1, 0),
+ RK_COMPNOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", 37, 0, 5, 8, 2, 0),
+ RK_COMPNOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", 37, 8, 5, 8, 3, 0),
+ RK_COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, 38, 6, 2, 0, 5, 8, 4, 0),
+ RK_COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, 38, 6, 2, 0, 5, 8, 4, 0),
+ RK_COMPNODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, 38, 15, 1, 8, 5, 0),
+ RK_COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, 39, 8, 2, 0, 8, 8, 6, 0),
+ RK_COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, 39, 8, 2, 0, 8, 8, 6, 0),
+ RK_COMPNODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, 39, 15, 1, 8, 7, 0),
+// RK_MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3308_SDMMC_CON0, 1),
+// RK_MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1),
+ RK_COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, 40, 8, 2, 0, 8, 8, 8, 0),
+ RK_COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, 40, 8, 2, 0, 8, 8, 8, 0),
+ RK_COMPNODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, 40, 15, 1, 8, 9, 0),
+// RK_MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3308_SDIO_CON0, 1),
+// RK_MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3308_SDIO_CON1, 1),
+ RK_COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, 41, 8, 2, 0, 8, 8, 10, 0),
+ RK_COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, 41, 8, 2, 0, 8, 8, 10, 0),
+ RK_COMPNODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, 41, 15, 1, 8, 11, 0),
+// RK_MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3308_EMMC_CON0, 1),
+// RK_MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK3308_EMMC_CON1, 1),
+ RK_COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 42, 14, 2, 0, 7, 8, 12, 0),
+ RK_MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, 2, 8, 2, 0),
+ RK_COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 43, 6, 2, 0, 5, 8, 14, 0),
+ RK_MUX(SCLK_MAC, "clk_mac", mux_mac_p, 43, 14, 1, 0),
+ RK_FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 1, 2),
+ RK_FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 1, 20),
+ RK_MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, 43, 15, 1, 0),
+ RK_COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 44, 14, 2, 8, 6, 8, 15, 0),
+ RK_COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, 1, 6, 2, 0, 3, 0, 10, 0),
+ RK_FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x",0,1, 4, 0, 13,0),
+ RK_COMPNODIV(0, "clk_ddrstdby", mux_ddrstdby_p, 1, 8, 1, 4, 14, 0),
+ RK_FRACTION(0, "clk_rtc32k_frac", "xin24m", 3, 4, 3, 0),
+ RK_MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 2, 10, 1, 0),
+ RK_COMPNOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", 4, 0, 16, 4, 2, 0),
+ RK_COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 72, 6, 1, 0, 6, 4, 7, 0),
+ RK_COMPNODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, 72, 7, 1, 4, 8, 0),
+ RK_COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 44, 6, 1, 0, 6, 4, 0, 0),
+ RK_COMPNODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, 44, 7, 1, 4, 1, 0),
+ RK_COMPNODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 45, 6, 2, 10, 0, 0),
+ RK_COMPNOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 45, 0, 5, 10, 1, 0),
+ RK_COMPNOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 45, 8, 5, 10, 2, 0),
+ RK_COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 46, 8, 2, 0, 7, 10, 3, 0),
+ RK_FRACTION(0, "clk_pdm_frac", "clk_pdm_src", 47, 10, 4, 0),
+ RK_MUX(0, "clk_pdm_mux", mux_pdm_p, 46, 15, 1, 0),
+ RK_COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 52, 8, 2, 0, 7, 10, 12, 0),
+ RK_FRACTION(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", 53, 10, 13, 0),
+ RK_COMPNODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, 52, 12, 1, 10, 14, 0),
+ RK_COMPNODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, 52, 15, 1, 10, 15, 0),
+ RK_COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 54, 8, 2, 0, 7, 11, 0, 0),
+ RK_FRACTION(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", 55, 11, 1, 0),
+ RK_COMPNODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, 54, 12, 1, 11, 2, 0),
+ RK_COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 56, 8, 2, 0, 7, 11, 4, 0),
+ RK_FRACTION(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", 57, 11, 5, 0),
+ RK_COMPNODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, 56, 12, 1, 11, 6, 0),
+ RK_COMPNODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, 56, 15, 1, 11, 7, 0),
+ RK_COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 58, 8, 2, 0, 7, 11, 8, 0),
+ RK_FRACTION(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", 59, 11, 9, 0),
+ RK_COMPNODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, 58, 12, 1, 11, 10, 0),
+ RK_COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 60, 8, 2, 0, 7, 11, 12, 0),
+ RK_FRACTION(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", 61, 11, 13, 0),
+ RK_COMPNODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, 60, 12, 1, 11, 14, 0),
+ RK_COMPNODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, 60, 15, 1, 11, 15, 0),
+ RK_COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 62, 8, 2, 0, 7, 12, 0, 0),
+ RK_FRACTION(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", 63, 12, 1, 0),
+ RK_COMPNODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, 62, 12, 1, 12, 2, 0),
+ RK_COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 64, 8, 2, 0, 7, 12, 4, 0),
+ RK_FRACTION(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", 65, 12, 5, 0),
+ RK_COMPNODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, 64, 12, 1, 12, 6, 0),
+ RK_COMPNODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, 64, 15, 1, 12, 7, 0),
+ RK_COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 66, 8, 2, 0, 7, 12, 8, 0),
+ RK_FRACTION(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", 67, 12, 9, 0),
+ RK_COMPNODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, 66, 12, 1, 12, 10, 0),
+ RK_COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 68, 8, 2, 0, 7, 12, 12, 0),
+ RK_FRACTION(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", 69, 12, 13, 0),
+ RK_COMPNODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, 68, 15, 1, 12, 15, 0),
+ RK_COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 70, 8, 2, 0, 7, 13, 0, 0),
+ RK_FRACTION(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", 71, 13, 1, 0),
+ RK_COMPNODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, 70, 15, 1, 13, 3, 0),
+ RK_COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, 48, 8, 2, 0, 7, 10, 6, 0),
+ RK_COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, 48, 8, 2, 0, 7, 10, 6, 0),
+ RK_MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, 48, 12, 1, 0),
+ RK_FRACTION(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", 49, 10, 7, 0),
+ RK_COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, 50, 8, 2, 0, 7, 10, 9, 0),
+ RK_COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, 50, 8, 2, 0, 7, 10, 9, 0),
+ RK_MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, 50, 14, 1, 0),
+ RK_FRACTION(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", 51, 10, 10, 0),
+ RK_FACTOR(ACLK_DMAC0, "aclk_dmac0", "aclk_bus", 1, 1),
+ RK_FACTOR(ACLK_DMAC1, "aclk_dmac1", "aclk_bus", 1, 1),
+ RK_FACTOR(PCLK_WDT, "pclk_wdt", "pclk_bus", 1, 1),
+ RK_MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, 52, 10, 2, 0),
+ RK_MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, 54, 10, 2, 0),
+ RK_MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, 56, 10, 2, 0),
+ RK_MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, 58, 10, 2, 0),
+ RK_MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, 60, 10, 2, 0),
+ RK_MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, 62, 10, 2, 0),
+ RK_MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, 64, 10, 2, 0),
+ RK_MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, 66, 10, 2, 0),
+ RK_MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, 68, 10, 2, 0),
+ RK_MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, 70, 10, 2, 0),
+ RK_MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, 48, 14, 2, 0),
+ RK_MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, 50, 15, 1, 0),
+};
+
+/* GATES */
+static struct rk_cru_gate rk3308_gates[] = {
+ RK_GATE(0, "apll_core", "apll", 0, 0),
+ RK_GATE(0, "vpll0_core", "vpll0", 0, 0),
+ RK_GATE(0, "vpll1_core", "vpll1", 0, 0),
+// RK_GATE(0, "clk_jtag", "jtag_clkin", 0, 3),
+ RK_GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0, 4),
+ RK_GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", 4, 15),
+ RK_GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 1, 12),
+ RK_GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 2, 0),
+ RK_GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 2, 4),
+ RK_GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 2, 8),
+ RK_GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 2, 12),
+ RK_GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 3, 10),
+ RK_GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 3, 11),
+ RK_GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 3, 12),
+ RK_GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 3, 13),
+ RK_GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 3, 14),
+ RK_GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 3, 15),
+ RK_GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 3, 9),
+ RK_GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 1, 8),
+ RK_GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 8, 13),
+ RK_GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 9, 1),
+ RK_GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 9, 0),
+ RK_GATE(0, "clk_ddr_mon_timer", "xin24m", 0, 12),
+ RK_GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", 4, 10),
+ RK_GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", 4, 11),
+ RK_GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", 4, 12),
+ RK_GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", 4, 13),
+ RK_GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", 0, 11),
+ RK_GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", 4, 5),
+ RK_GATE(SCLK_PMU, "clk_pmu", "pclk_bus", 4, 6),
+ RK_GATE(0, "clk_wifi_dpll", "dpll", 15, 2),
+ RK_GATE(0, "clk_wifi_vpll0", "vpll0", 15, 3),
+ RK_GATE(0, "clk_wifi_osc", "xin24m", 15, 4),
+ RK_GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 4, 4),
+ RK_GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 10, 5),
+ RK_GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 11, 3),
+ RK_GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 11, 11),
+ RK_GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 12, 3),
+ RK_GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 12, 11),
+ RK_GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 12, 14),
+ RK_GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 13, 2),
+ RK_GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 10, 8),
+ RK_GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 10, 11),
+ RK_GATE(0, "aclk_core_niu", "aclk_core", 0, 5),
+ RK_GATE(0, "pclk_core_dbg_niu", "aclk_core", 0, 6),
+ RK_GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", 0, 7),
+ RK_GATE(0, "aclk_core_perf", "pclk_core_dbg", 0, 8),
+ RK_GATE(0, "pclk_core_grf", "pclk_core_dbg", 0, 9),
+ RK_GATE(0, "aclk_peri_niu", "aclk_peri", 9, 2),
+ RK_GATE(0, "aclk_peribus_niu", "aclk_peri", 9, 3),
+ RK_GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 9, 4),
+ RK_GATE(0, "hclk_peri_niu", "hclk_peri", 9, 5),
+ RK_GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 9, 6),
+ RK_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 9, 7),
+ RK_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 9, 8),
+ RK_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 9, 9),
+ RK_GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 9, 10),
+ RK_GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 9, 11),
+ RK_GATE(HCLK_HOST, "hclk_host", "hclk_peri", 9, 12),
+ RK_GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 9, 13),
+ RK_GATE(0, "pclk_peri_niu", "pclk_peri", 9, 14),
+ RK_GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 9, 15),
+ RK_GATE(0, "hclk_audio_niu", "hclk_audio", 14, 0),
+ RK_GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 14, 1),
+ RK_GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 14, 2),
+ RK_GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 14, 3),
+ RK_GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 14, 4),
+ RK_GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 14, 5),
+ RK_GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 14, 6),
+ RK_GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 14, 7),
+ RK_GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 14, 8),
+ RK_GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 14, 9),
+ RK_GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 14, 10),
+ RK_GATE(0, "pclk_audio_niu", "pclk_audio", 14, 11),
+ RK_GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 14, 12),
+ RK_GATE(0, "aclk_bus_niu", "aclk_bus", 5, 0),
+ RK_GATE(0, "aclk_intmem", "aclk_bus", 5, 1),
+ RK_GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 5, 2),
+ RK_GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 5, 3),
+ RK_GATE(0, "aclk_gic", "aclk_bus", 5, 4),
+ RK_GATE(0, "hclk_bus_niu", "hclk_bus", 5, 5),
+ RK_GATE(0, "hclk_rom", "hclk_bus", 5, 6),
+ RK_GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 5, 7),
+ RK_GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 5, 8),
+ RK_GATE(0, "pclk_bus_niu", "pclk_bus", 5, 9),
+ RK_GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 5, 10),
+ RK_GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 5, 11),
+ RK_GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 5, 12),
+ RK_GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 5, 13),
+ RK_GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 5, 14),
+ RK_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 5, 15),
+ RK_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 6, 0),
+ RK_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 6, 1),
+ RK_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 6, 2),
+ RK_GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 6, 3),
+ RK_GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 6, 4),
+ RK_GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 6, 5),
+ RK_GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 6, 6),
+ RK_GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 6, 7),
+ RK_GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 6, 8),
+ RK_GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 6, 9),
+ RK_GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 6, 10),
+ RK_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 6, 12),
+ RK_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 6, 13),
+ RK_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 6, 14),
+ RK_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 6, 15),
+ RK_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 7, 0),
+ RK_GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", 7, 1),
+ RK_GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 7, 2),
+ RK_GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", 7, 3),
+ RK_GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", 7, 4),
+ RK_GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", 7, 5),
+ RK_GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 7, 6),
+ RK_GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", 7, 7),
+ RK_GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", 7, 8),
+ RK_GATE(PCLK_CRU, "pclk_cru", "pclk_bus", 7, 9),
+ RK_GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 7, 10),
+ RK_GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", 7, 11),
+ RK_GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 7, 12),
+ RK_GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 7, 13),
+ RK_GATE(PCLK_CAN, "pclk_can", "pclk_bus", 7, 14),
+ RK_GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", 7, 15),
+};
+
+
+static int
+rk3308_cru_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (ofw_bus_is_compatible(dev, "rockchip,rk3308-cru")) {
+ device_set_desc(dev, "Rockchip RK3308 Clock & Reset Unit");
+ return (BUS_PROBE_DEFAULT);
+ }
+ return (ENXIO);
+}
+
+static int
+rk3308_cru_attach(device_t dev)
+{
+ struct rk_cru_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ sc->clks = rk3308_clks;
+ sc->nclks = nitems(rk3308_clks);
+ sc->gates = rk3308_gates;
+ sc->ngates = nitems(rk3308_gates);
+ sc->reset_offset = 0x400;
+ sc->reset_num = 478;
+
+ return (rk_cru_attach(dev));
+}
+
+static device_method_t methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, rk3308_cru_probe),
+ DEVMETHOD(device_attach, rk3308_cru_attach),
+
+ DEVMETHOD_END
+};
+
+DEFINE_CLASS_1(rk3308_cru, rk3308_cru_driver, methods,
+ sizeof(struct rk_cru_softc), rk_cru_driver);
+
+EARLY_DRIVER_MODULE(rk3308_cru, simplebus, rk3308_cru_driver,
+ 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
Index: sys/conf/files.arm64
===================================================================
--- sys/conf/files.arm64
+++ sys/conf/files.arm64
@@ -685,6 +685,7 @@
arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568
arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568
arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 | fdt soc_rockchip_rk3568
+arm64/rockchip/clk/rk3308_cru.c optional fdt soc_rockchip_rk3308
arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328
arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399

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