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Index: sys/dev/iommu/busdma_iommu.c
===================================================================
--- sys/dev/iommu/busdma_iommu.c
+++ sys/dev/iommu/busdma_iommu.c
@@ -299,7 +299,7 @@
}
bool
-bus_dma_dmar_set_buswide(device_t dev)
+bus_dma_iommu_set_buswide(device_t dev)
{
struct iommu_unit *unit;
device_t parent;
@@ -317,12 +317,12 @@
if (slot != 0 || func != 0) {
if (bootverbose) {
device_printf(dev,
- "dmar%d pci%d:%d:%d requested buswide busdma\n",
+ "iommu%d pci%d:%d:%d requested buswide busdma\n",
unit->unit, busno, slot, func);
}
return (false);
}
- dmar_set_buswide_ctx(unit, busno);
+ iommu_set_buswide_ctx(unit, busno);
return (true);
}
Index: sys/dev/iommu/iommu.h
===================================================================
--- sys/dev/iommu/iommu.h
+++ sys/dev/iommu/iommu.h
@@ -40,6 +40,8 @@
#include <sys/tree.h>
#include <sys/types.h>
+#include <dev/pci/pcireg.h>
+
/* Host or physical memory address, after translation. */
typedef uint64_t iommu_haddr_t;
/* Guest or bus address, before translation. */
@@ -96,6 +98,14 @@
struct task dmamap_load_task;
TAILQ_HEAD(, bus_dmamap_iommu) delayed_maps;
struct taskqueue *delayed_taskqueue;
+
+ /*
+ * Bitmap of buses for which context must ignore slot:func,
+ * duplicating the page table pointer into all context table
+ * entries. This is a client-controlled quirk to support some
+ * NTBs.
+ */
+ uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
};
/*
Index: sys/dev/ntb/ntb_hw/ntb_hw_plx.c
===================================================================
--- sys/dev/ntb/ntb_hw/ntb_hw_plx.c
+++ sys/dev/ntb/ntb_hw/ntb_hw_plx.c
@@ -343,7 +343,7 @@
* The device occupies whole bus. In translated TLP slot field
* keeps LUT index (original bus/slot), function is passed through.
*/
- bus_dma_dmar_set_buswide(dev);
+ bus_dma_iommu_set_buswide(dev);
/* Identify chip port we are connected to. */
val = bus_read_4(sc->conf_res, 0x360);
Index: sys/x86/include/bus_dma.h
===================================================================
--- sys/x86/include/bus_dma.h
+++ sys/x86/include/bus_dma.h
@@ -192,7 +192,7 @@
}
#ifdef _KERNEL
-bool bus_dma_dmar_set_buswide(device_t dev);
+bool bus_dma_iommu_set_buswide(device_t dev);
int bus_dma_dmar_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map,
vm_paddr_t start, vm_size_t length, int flags);
#endif
Index: sys/x86/iommu/intel_ctx.c
===================================================================
--- sys/x86/iommu/intel_ctx.c
+++ sys/x86/iommu/intel_ctx.c
@@ -196,7 +196,7 @@
IOMMU_PGF_NOALLOC);
}
- if (dmar_is_buswide_ctx(unit, busno)) {
+ if (iommu_is_buswide_ctx((struct iommu_unit *)unit, busno)) {
MPASS(!move);
for (i = 0; i <= PCI_BUSMAX; i++) {
ctx_id_entry_init_one(&ctxp[i], domain, ctx_root);
@@ -464,6 +464,7 @@
{
struct dmar_domain *domain, *domain1;
struct dmar_ctx *ctx, *ctx1;
+ struct iommu_unit *unit;
dmar_ctx_entry_t *ctxp;
struct sf_buf *sf;
int bus, slot, func, error;
@@ -480,9 +481,10 @@
}
enable = false;
TD_PREP_PINNED_ASSERT;
+ unit = (struct iommu_unit *)dmar;
DMAR_LOCK(dmar);
- KASSERT(!dmar_is_buswide_ctx(dmar, bus) || (slot == 0 && func == 0),
- ("dmar%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
+ KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0),
+ ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus,
slot, func));
ctx = dmar_find_ctx_locked(dmar, rid);
error = 0;
Index: sys/x86/iommu/intel_dmar.h
===================================================================
--- sys/x86/iommu/intel_dmar.h
+++ sys/x86/iommu/intel_dmar.h
@@ -167,15 +167,6 @@
struct iommu_map_entries_tailq tlb_flush_entries;
struct task qi_task;
struct taskqueue *qi_taskqueue;
-
- /*
- * Bitmap of buses for which context must ignore slot:func,
- * duplicating the page table pointer into all context table
- * entries. This is a client-controlled quirk to support some
- * NTBs.
- */
- uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)];
-
};
#define DMAR_LOCK(dmar) mtx_lock(&(dmar)->iommu.lock)
@@ -290,8 +281,8 @@
int dmar_init_irt(struct dmar_unit *unit);
void dmar_fini_irt(struct dmar_unit *unit);
-void dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno);
-bool dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno);
+void iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno);
+bool iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno);
extern iommu_haddr_t dmar_high;
extern int haw;
Index: sys/x86/iommu/intel_drv.c
===================================================================
--- sys/x86/iommu/intel_drv.c
+++ sys/x86/iommu/intel_drv.c
@@ -593,21 +593,18 @@
MODULE_DEPEND(dmar, acpi, 1, 1, 1);
void
-dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
+iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
{
- struct dmar_unit *dmar;
-
- dmar = (struct dmar_unit *)unit;
MPASS(busno <= PCI_BUSMAX);
- DMAR_LOCK(dmar);
- dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
+ IOMMU_LOCK(unit);
+ unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |=
1 << (busno % (NBBY * sizeof(uint32_t)));
- DMAR_UNLOCK(dmar);
+ IOMMU_UNLOCK(unit);
}
bool
-dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)
+iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno)
{
MPASS(busno <= PCI_BUSMAX);
Index: sys/x86/x86/busdma_machdep.c
===================================================================
--- sys/x86/x86/busdma_machdep.c
+++ sys/x86/x86/busdma_machdep.c
@@ -301,7 +301,7 @@
#ifndef ACPI_DMAR
bool
-bus_dma_dmar_set_buswide(device_t dev)
+bus_dma_iommu_set_buswide(device_t dev)
{
return (false);
}

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