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Index: sys/dev/ichiic/ig4_pci.c
===================================================================
--- sys/dev/ichiic/ig4_pci.c
+++ sys/dev/ichiic/ig4_pci.c
@@ -80,73 +80,63 @@
#define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086
#define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086
#define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086
+#define PCI_CHIP_APL_I2C_0 0x5aac8086
+#define PCI_CHIP_APL_I2C_1 0x5aae8086
+#define PCI_CHIP_APL_I2C_2 0x5ab08086
+#define PCI_CHIP_APL_I2C_3 0x5ab28086
+#define PCI_CHIP_APL_I2C_4 0x5ab48086
+#define PCI_CHIP_APL_I2C_5 0x5ab68086
+#define PCI_CHIP_APL_I2C_6 0x5ab88086
+#define PCI_CHIP_APL_I2C_7 0x5aba8086
+struct ig4iic_pci_device {
+ uint32_t devid;
+ const char *desc;
+ enum ig4_vers version;
+};
+
+static struct ig4iic_pci_device ig4iic_pci_devices[] = {
+ { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
+ { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
+ { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM},
+ { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM},
+ { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM},
+ { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM},
+ { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM},
+ { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM},
+ { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
+ { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
+ { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
+ { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
+ { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
+ { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_SKYLAKE},
+ { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_SKYLAKE},
+ { 0, NULL, 0 },
+};
+
static int
ig4iic_pci_probe(device_t dev)
{
ig4iic_softc_t *sc = device_get_softc(dev);
+ uint32_t devid;
+ int i;
- switch(pci_get_devid(dev)) {
- case PCI_CHIP_LYNXPT_LP_I2C_1:
- device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-1");
- sc->version = IG4_HASWELL;
- break;
- case PCI_CHIP_LYNXPT_LP_I2C_2:
- device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2");
- sc->version = IG4_HASWELL;
- break;
- case PCI_CHIP_BRASWELL_I2C_1:
- device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 1");
- sc->version = IG4_ATOM;
- break;
- case PCI_CHIP_BRASWELL_I2C_2:
- device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 2");
- sc->version = IG4_ATOM;
- break;
- case PCI_CHIP_BRASWELL_I2C_3:
- device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 3");
- sc->version = IG4_ATOM;
- break;
- case PCI_CHIP_BRASWELL_I2C_5:
- device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5");
- sc->version = IG4_ATOM;
- break;
- case PCI_CHIP_BRASWELL_I2C_6:
- device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6");
- sc->version = IG4_ATOM;
- break;
- case PCI_CHIP_BRASWELL_I2C_7:
- device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7");
- sc->version = IG4_ATOM;
- break;
- case PCI_CHIP_SKYLAKE_I2C_0:
- device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-0");
- sc->version = IG4_SKYLAKE;
- break;
- case PCI_CHIP_SKYLAKE_I2C_1:
- device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-1");
- sc->version = IG4_SKYLAKE;
- break;
- case PCI_CHIP_SKYLAKE_I2C_2:
- device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-2");
- sc->version = IG4_SKYLAKE;
- break;
- case PCI_CHIP_SKYLAKE_I2C_3:
- device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-3");
- sc->version = IG4_SKYLAKE;
- break;
- case PCI_CHIP_SKYLAKE_I2C_4:
- device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-4");
- sc->version = IG4_SKYLAKE;
- break;
- case PCI_CHIP_SKYLAKE_I2C_5:
- device_set_desc(dev, "Intel Sunrise Point-LP I2C Controller-5");
- sc->version = IG4_SKYLAKE;
- break;
- default:
- return (ENXIO);
+ devid = pci_get_devid(dev);
+ for (i = 0; ig4iic_pci_devices[i].devid != 0; i++) {
+ if (ig4iic_pci_devices[i].devid == devid) {
+ device_set_desc(dev, ig4iic_pci_devices[i].desc);
+ sc->version = ig4iic_pci_devices[i].version;
+ return (BUS_PROBE_DEFAULT);
+ }
}
- return (BUS_PROBE_DEFAULT);
+ return (ENXIO);
}
static int
Index: sys/dev/ichiic/ig4_var.h
===================================================================
--- sys/dev/ichiic/ig4_var.h
+++ sys/dev/ichiic/ig4_var.h
@@ -47,7 +47,7 @@
#define IG4_RBUFMASK (IG4_RBUFSIZE - 1)
enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE };
-enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE };
+enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL };
struct ig4iic_softc {
device_t dev;

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